SK Hynix Inc. announced the completion of developing the industry’s most multilayered 176-layer 512 Gigabit (Gb) Triple-Level Cell (TLC) 4D NAND flash. The Company provided the samples to controller companies last month to make a solution product.
SK Hynix has been promoting 4D technology from the 96-layer NAND flash products that combine Charge Trap Flash (CTF) with high-integrated Peri. Under Cell (PUC) technology. The new 176-layer NAND flash is the third generation 4D product that secures the industry’s best number of chips per wafer. This allows the bit productivity to be improved by 35% compared to the previous generation with the differentiated cost competitiveness. The read speed of cells increased by 20% over the previous generation adopting 2-division cell array selection technology. The data transfer speed also has been improved by 33% to 1.6Gbps adopting speed-up technology without increasing the number of processes.
Starting with mobile solution products that have improved maximum read speed by 70% and maximum write speed by 35% in the middle of next year, SK Hynix plans to release consumer and enterprise SSDs sequentially expanding its application market of the products.
As the number of layers increases in NAND flash, the cell current reduction, the channel hole twisting, and the cell distribution deterioration due to double-stack misalignment occurs. SK Hynix overcame these challenges by adopting innovative technologies such as cell interlayer height reduction, layer variable timing control, and ultra-precise alignment and developed the industry’s top tier 176-layer NAND flash.
The Company also plans to consistently enhance its competitiveness in the NAND flash business by developing 1 Terabit (Tb) products with doubled density based on 176-layer 4D NAND.
According to market intelligence provider Omdia, the NAND flash market is estimated to expand from 431.8 billion GB in 2020 to 1.366 trillion GB in 2024 with a 33.4 percent Compound Annual Growth Rate (CAGR).
SK Hynix has named ‘4D NAND Flash’ to highlight the differentiation that achieves both performance and productivity at the same time by combining CTF cell structure and PUC technology from 96-layer NAND Flash in 2018.
Charge Trap Flash (CTF)
Unlike floating gate, which stores electric charges in conductors, CTF stores electric charges in insulators, which eliminates interference between cells, improving read and write performance while reducing cell area per unit compared to floating gate technology. Most 3D NAND companies are adopting CTF.
Peri. Under Cell (PUC)
A technology that maximizes production efficiency by placing peripheral circuits under the cell array.
2-division cell array selection technology
The word line applies a voltage to the cell in the NAND flash circuit. The more the number of layers, the thinner the word line is to lower the cell’s height, and the greater the resistance applied to the word line will affect the speed. By dividing the cell connected to the word line into half compared to the existing one, the resistance can be lowered, which shortens the time of applying voltage and improves the read speed.
Cell interlayer height reduction technology
As the number of layers increases, it becomes difficult to drill holes for cell formation. This leads to increased resistance and reduced current, making it difficult to secure performance and reliability. For this, it is necessary to lower the cell interlayer height as much as possible, but this can increase interference between cells and defect rate. The cell interlayer height reduction technology not only dramatically lowered the cell interlayer height of 176-layers but also secured competitive performance/reliability with related processes and design technologies.
Layer variable timing control technology
Increasing the number of layers and lowering the layer height often leads to channel hole twisting and cell scattering deterioration, which degrades the performance and reliability of each layer. This technology adjusts the amount and time of voltage applied according to the characteristics of each layer to maintain uniform cell characteristics and improve performance and reliability.
Ultra-precise alignment technology
Industries are utilizing a double-stack process that drills holes twice because it is impossible to drill holes for cell formation at once as the number of layers increases. Minimizing double-stack misalignment is the core of double-stack technology. If the stacks are not aligned correctly, it will result in poor flow of current between stacks and occurrence of deterioration, reducing yield rate, performance, and reliability. SK Hynix applied double-stack technology since its 72-layer product in 2017, to this 176-layer product and advanced a technology that automatically corrects the location and size of holes in real-time based on its know-how.