SiFive , announced the availability of U54-MC Coreplex IP, the industry’s first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full-featured operating systems such as Linux. The free and open RISC-V architecture, which is supported by an ecosystem comprising more than 70 companies, has seen tremendous growth in the embedded segment. The release of […]
RISC-V
Webinar: The RISC-V ecosystem is ready for prime time. Get started here! – October 25
Wednesday, October 25, 2017 2:00pm EDT / 11:00am PST The RISC-V ISA (instruction set architecture) is redefining the embedded processor marketplace. The open architecture of the RISC-V ecosystem has developed critical mass. Be on the leading edge of what is the next big thing. Attend this webinar to learn about: Fixed ISA allows customization for […]
Debug and trace technology added to open-source RISC-V CPU platform
SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC’s embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any […]
Eclipse integrated development environment targets RISC-V open instruction set designs
Microsemi Corporation announced the release of its SoftConsole version 5.1, the world’s first available Windows-hosted Eclipse integrated development environment (IDE) for designs utilizing RISC-V open instruction set architectures (ISAs) such as RV32I. SoftConsole, Microsemi’s free software development environment enabling rapid production of C and C++ programming language designs for its field programmable gate arrays (FPGAs), will be showcased at […]
