SEGGER’s emRun++ is a groundbreaking C++ library, fully compatible with the modern 2017 standard. It is used and proven in SEGGER’s multi-platform Embedded Studio IDE for RISC-V and Arm and is now available for licensing to toolchain vendors. emRun++ guarantees fast heap operations with a low instruction count limit, enabling even hard real-time applications to […]
RISC-V
Neuromorphic AI runs on multi-core RISC-V processors
BrainChip Holdings Ltd and SiFive, Inc. have combined their respective technologies to offer chip designers optimized AI/ML compute at the edge. BrainChip’s Akida is a revolutionary advanced neural networking processor architecture that brings AI to the edge in a way that existing technologies are not capable of, with high performance, ultra-low power, and on-chip learning. […]
Software development kit features and real-time C++ support for RISC-V
SEGGER’s Embedded Studio for RISC-V, Version 6, now uses real-time memory management which improves efficiency and response time when allocating and freeing up memory, satisfying requirements for hard real-time in applications written in C++. The new version supports all common RISC-V 32-bit and 64-bit cores, including but not limited to RV64I, RV64E, RV64GC, RV32I, RV32IMA, RV32IMAC, […]
IP core modules facilitate reuse of SoC, MCU, FPGA and ASIC functions
The Fraunhofer Institute for Photonic Microsystems IPMS offers ready-made, platform-independent IP core modules. With IP modules, developers can quickly adopt complete functional areas in standard products such as SoCs, microcontrollers, FPGAs and ASICs. This allows a significant reduction of development times and costs. With EMSA5, Fraunhofer IPMS offers a processor core based on the open […]
Compiler/debugger supports 64-bit RISC-V cores
IAR Systems proudly presented support for 64-bit RISC-V cores in the professional development toolchain IAR Embedded Workbench for RISC-V. With this extended core support, IAR Systems continues to be at the forefront of providing professional development solutions for RISC-V. IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain with everything embedded […]
C/C++ development environment works with RISC-V MCUs
SEGGER announces its partnership with HPMicro Semiconductor Inc. The partnership focuses on making SEGGER’s top-rated, multi-platform IDE Embedded Studio available, free of charge, to all HPMicro’s customers using HPM6000 series RISC-V microcontrollers, boosting the RISC-V ecosystem. Embedded Studio includes all the tools and features expected for streamlined, professional embedded development in C and C++. It comes […]
Test suites for RISC-V now available for high quality security applications
Imperas Software Ltd. announced the beta release of the ImperasDV architectural validation test suites for RISC-V Physical Memory Protection (PMP). The open standard ISA (Instruction Set Architecture) of RISC-V offers developers a wide range of standard extensions and options that support the design of an optimized processor while leveraging the ecosystem of compatibility. The RISC-V Privileged […]
Updated RISC-V processor IP portfolio targets mid-range application capable and real-time processors
SiFive, Inc. announced the availability of the SiFive 21G3 release, a comprehensive suite of product updates for the industry’s broadest and most successful RISC-V processor IP portfolio, and introduced the new SiFive Essential 6-Series range of RISC-V processor IP to address market demands for mid-range application capable and real-time processors. With the new SiFive Essential […]
C++ compiler/debugger handles low-power embedded processors
IAR Systems and Codasip announced their partnership enabling joint customers to build low-power embedded applications based on RISC-V. Following this, version 2.11 of IAR Embedded Workbench for RISC-V now supports the L30 and L50 processors from Codasip. The L30 and L50 are small and energy-efficient low-power embedded processor cores from Codasip, all fully customizable and […]
Tiny processor IP core uses the open-source RISC-V
The 32-bit BA51 Low-Power Deeply Embedded RISC-V Processor IP core uses the open-source RISC-V instruction set and offers low power consumption, small silicon area, and configurable options for optimally running many embedded applications. It implements a two-stage pipeline, is compact – just 16k gates in its minimum configuration – but can still run at over […]