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Top microcontroller stories of 2017

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microcontrollerHere are the microcontroller features that got the most interest from readers in 2017.

 

What is an open drain?
Open-collector and -drain devices sink current when controlled to one state and have no current flow (i.e., output a high impedance state) in the other state. It is fairly common to use open-drains (open-collectors) together with a pull-up resistor.

What are compilers, translators, interpreters, and assemblers?
Translators, compilers, interpreters and assemblers are all software programming tools that convert code into another type of code, but each term has specific meaning. All of the above work in some way towards getting a high-level programming language translated into machine code that the central processing unit (CPU) can understand.

MOSFETs: What is RDS(on)?
Besides these inherent structural contributors to RDS(on), imperfect contact between the source and drain metal and even the wiring that connects the die to the leads on the package can also contribute to RDS(on).

Debouncing switches in hardware and software
When an MCU is polling a digital input several times a second it can very easily register that the switch or button has changed state rapidly between 0 and 1 a few times within a few milliseconds. This can cause the switch to register an on/off status for which the total count of status changes would be grossly incorrect.

RISC architecture and instruction architecture
The difference between architectures can be found in how tasks are completed, such as how a specific architecture handles registers, interrupts, memory addressing, external inputs and outputs, and so forth.

What is differential signaling?
Differential signaling is more immune to noise and it is faster. The difference in voltage level between the two signals is what determines whether the pulse is a 1 or a 0. There is still a rise and a fall time associated with each signal, but differential signaling can have lower voltages and a faster switching time.

What is an embedded bootloader?
 A bootloader is necessary for starting processors at the lowest level before starting an operating system (e.g., a computer) or presenting a command line (e.g., an MCU). 

Teardown: Inside the Anki Overdrive racecar set
Removing the top of a car exposes the circuit board, the chassis, and a large ballast weight. The PCB sits in the chassis sandwiched between the two halves of the car shell so it comes out easily.

ADAS developers contemplate sensor fusion
Vision is an increasingly important facet of vehicle technology. Vision sensors now support active safety features that include everything from rear-view cameras to forward-looking and in-cabin ADAS.

What is I2C, a.k.a. “I-squared-C”?
Integrated chips that integrate I2C capability cover many different applications and devices. For instance, a majority of sensor ICs incorporate I2C communication into their circuitry, as long as I2C data transfer rates are sufficient for a control loop’s purposes.

Free BOM calculator for custom IC costs

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S3 Semiconductors today announced an online bill of materials (BOM) calculator that shows how custom ICs are economically viable even in low to medium volumes. Learning from S3 Semiconductors’ 20 years of experience in designing custom ICs, the BOM calculator will provide an estimate of project development costs and give a guide to break-even volumes using just a few key data points. Such data includes shipment volumes, planned lifetime and technical information on the components required.

Aiming to disprove the myth that custom ICs are too expensive for designs requiring relatively small quantities, the calculator will be of particular interest to engineers engaged in Industrial Internet of Things (IIoT) developments. The data needs of the IIoT are responsible for increasing control system complexity, which in turn adds to the number of components used and the pressures on diminishing board space. The compound result of all these factors leads to difficulties in production, testing and inventory management.

Dermot Barry, VP and General Manager at S3 Semiconductors commented, ‘Custom control ICs offer many advantages over discrete designs. Not only do they use less power, but they also have no redundant features, simplify PCB design and offer increased security and IP protection. Custom ICs also help in making product differentiation much easier, as well as offering a solution to a growing problem for the electronics industry, that of component obsolescence’.

S3 Semiconductors has launched this free BOM calculator to simplify the process of costing a custom IC and give developers a quick and easy way to see break-even volumes for custom semiconductor designs without allocating any resources. In the process, the calculation will demonstrate how viable custom silicon is for low- to mid-volume designs.

The BOM calculator can be found at https://www.s3semi.com/bom-calculator/.

Additional Resources: The Compelling Economics for OEMs to Commission their own Semiconductor Chips

Chip design CAD software supports integrated fan-out advanced packaging, chip-on-wafer-on-substrate packaging technologies

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Mentor, a Siemens business, today announced several enhancements to its Calibre® nmPlatform, Analog FastSPICE™ (AFS™) Platform, Xpedition® Package Integrator and Xpedition Package Designer tools in support of TSMC’s innovative InFO integrated fan-out advanced packaging and CoWoS® chip-on-wafer-on-substrate packaging technologies.

The TSMC InFO and CoWoS 3D packaging technologies enable customers to mix multiple silicon dice on a single device and achieve higher levels of integration and capacity than traditional monolithic ICs.

Based on the Mentor Calibre and Xpedition platforms, a full InFO design-to-package verification and analysis suite is now available from Mentor. Key benefits include a fast design-to-tape-out flow based on the Xpedition Package Integrator’s rapid hierarchical design prototyping environment, with integrations to the Xpedition Package Designer and the Calibre sign-off verification suite. Additional collaboration extended the cross-probing capability between the Calibre 3DSTACK and Xpedition tools, with the results viewable within the Calibre RVE™ interface.

TSMC and Mentor also enabled the Mentor thermal flow (which includes the Mentor AFS and Calibre xACT™ offerings) to support thermal-aware simulation for customers’ InFO designs.

To enable package-level cross-die timing analysis, Mentor enhanced Xpedition Package Integrator to support a netlisting capability incorporated with Calibre xACT extraction results for InFO and CoWoS designers to verify timing requirements.

Reliability is a fundamental component of all design flows. As such, TSMC and Mentor developed stacked-die solutions based on the Mentor Calibre PERC™reliability platform for both TSMC’s InFO and CoWoS flows. This new offering addresses inter-die electrostatic discharge (ESD) analysis.

“Our collaboration with Mentor supports mutual customers to quickly realize the benefits of using TSMC’s InFO and CoWoS packaging solutions,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With Mentor’s design suite for TSMC InFO and CoWoS, customers in automotive, networking, high-performance computing (HPC), and numerous other markets can achieve new levels of integration.”

“We are honored to be working alongside our longtime partner TSMC to further refine and mature Mentor design solutions for InFO and CoWoS packaging technologies,” said Joe Sawicki, vice president and general manager, Mentor Design to Silicon. “Together we have helped make 3D-IC a viable mainstream alternative to monolithic IC design that is in enabling an ever-growing number of customers achieve truly remarkable world-changing innovations.”

Chip design CAD system supports 7-nm FinFET Plus and 12-nm FinFET process technologies

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Mentor, a Siemens business, today announced certification for TSMC’s 12nm FinFET Compact Technology (12FFC) and the latest version of 7nm FinFET Plus processes for its Mentor Calibre® nmPlatformand Analog FastSPICE™ (AFS™) Platform. Nitro-SoCTM place and route system is also certified to support TSMC’s 12FFC process technology.

“TSMC is pleased to work closely with Mentor, which continues to increase its value to the TSMC ecosystem by offering more features to its tool flow in support of our new 12nm and 7nm FinFET Plus processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Mentor has been a strategic partner for many years, and with Siemens’ commitment to further investments in Mentor’s electronic design automation (EDA) technologies, we look forward to helping our mutual customers bring to market new and even more amazing IC innovations.”

Mentor enhanced the Calibre nmDRC™ and Calibre nmLVS™ tools for the latest versions of TSMC’s 12nm and 7nm FinFET Plus processes. Mentor worked with TSMC to not only ensure appropriate coverage, but also to optimize the design kits for runtime performance. In addition, TSMC and Mentor worked together to make extreme ultraviolet (EUV) lithography requirements transparent to mutual customers within the Calibre design rule checking (DRC) and multi-patterning software.

Calibre xACT™ parasitic extraction tool is also certified for TSMC’s 12nm v1.0 and the latest version of 7nm FinFET Plus, achieving needed accuracy requirements.

The Calibre YieldEnhancer tool is not only certified for TSMC’s 12nm and 7nm FinFET Plus processes, but Mentor and TSMC are also jointly delivering enhanced use models that optimize fill runtimes, minimize shape removal through engineering change order (ECO) fill, and ensure consistency across all layers using fill-as-you-go methodologies.

The Calibre PERC™ reliability platform is the verification solution for both IP and full-chip reliability analysis. Point-to-point and current density reliability checks are critical for today’s complex, dense chip designs, but completing these checks on very large 12nm and 7nm FinFET Plus designs requires scalability. TSMC and Mentor collaborated to enable a Calibre PERC solution leveraging a new multi-CPU run capability that allows mutual customers to more quickly find and resolve full-chip reliability concerns in their designs.

The AFS platform, including the AFS Mega circuit simulator, is certified for the TSMC 12nm and TSMC 7nm FinFET Plus processes. The AFS platform supports all the required features for TSMC’s design platforms for mobile and HPC applications. Analog, mixed-signal and radio frequency (RF) design teams at leading semiconductor companies worldwide benefit from using the AFS platform to verify their chips designed in the latest TSMC technologies.

Mentor’s Nitro-SoCTM place and route system is certified for TSMC’s 12nm process. In addition to support for 12nm process rules, Mentor enhanced Nitro-SoC’s core engines to meet the new standard cell architecture requirements and design rules for this high-density, power-efficient process. This enables Mentor to deliver its digital implementation flow for the 12nm node.

“Mentor is pleased to be a key element of the TSMC ecosystem,” said Joe Sawicki, vice president and general manager, Mentor Design to Silicon. “This year, TSMC and Mentor are jointly delivering solutions that continue to provide our mutual customers with multiple design avenues to deliver IC innovations for the mobile, high-performance computing, automotive, and IoT/wearable markets.”