Synopsys, Inc. announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform. It has been optimized to provide maximum designer productivity for designers of advanced 5G, HPC, AI, and IoT applications using the Samsung 3nm GAA process technology.
Complexity at advanced nodes means designers are looking for new methods to shorten design cycles. Through close collaboration, Samsung and Synopsys provide a flow that is optimized to overcome design complexity and provide the best possible products for 3nm GAA design. Key features of the flow include in-design electromigration analysis, which shortens design closure time by providing accurate electromigration analysis before the layout is complete. It also includes Live design rule checking (DRC) with Synopsys’ IC Validator physical verification solution, enabling layout engineers to quickly check for design rule violations directly from the layout canvas as they work.
The AMS reference flow provides a proven methodology for designing at 3nm GAA process technology. This methodology, which has been validated by Samsung, includes a full set of documented flows and design examples. Covered topics include design entry, circuit simulation, Monte Carlo analysis, noise analysis, RF analysis, aging, and EM/IR analysis, parasitic simulation, layout, and signoff.
The Synopsys Custom Design Platform is based on the Custom Compiler design and layout environment and includes HSPICE circuit simulator, FineSim circuit simulator, CustomSim FastSPICE circuit simulator, Custom WaveView waveform display, StarRC parasitic extraction, and IC Validator physical verification. The platform features natively integrated StarRC extraction to provide early feedback on the impact of parasitics on circuit behavior, performance, and pioneering visually-assisted layout automation capabilities that simplify the creation of advanced-node layout.