by Mark Puttock, Director Advanced Deposition and Plating, office of CTO, Entegris

Even as 3D NAND races toward maturity and becomes a mainstream technology, chipmakers know there is still more to achieve to meet worldwide consumer and business data demands at lower costs, given the extreme complexities involved.

As with previous technologies, focusing on process efficiencies, materials innovations, and contamination control will optimize manufacturing processes, resulting in better performance, increased yield, and reduced costs.

Optimize high-aspect-ratio etching through materials development

Creating complex 3D structures with very high-aspect-ratio (HAR) features is complicated and requires extreme precision and, ultimately, process uniformity and repeatability to achieve scale.

Precision in etching extreme HAR features is critical for optimizing channel holes and trenches for cell access, as well as its unique staircase structure architecture, which connects the cells to the surrounding CMOS circuitry for reading, writing, and erasing data.

One example of an Etch challenge is the hard mask material typically used for HAR etching. It’s typically amorphous carbon, and its job is to protect patterned areas of material while allowing features to be exposed to Plasma Etching based material removal, but it’s reaching the limit as it is not plasma-resistant enough to do this job as aspect ratios increase. Some of the possible solutions to this challenge will require innovative new materials and development measures to bring higher resistance, stability, repeatability, and optimization to critical etch processes.

If the vertical pitch of the memory stack is around 50 nm, then a 96-layer stack of cells is in the order of 4.8 μm high. This corresponds to a challenging aspect ratio of ~100:1. In addition, as the cell stack comprises stacked pairs of silicon nitride (Si3N4) at the cell level and silicon dioxide (SiO2) to isolate cells, it is extremely difficult for dry etch engineers to achieve a continuous and straight profile while maintaining high enough selectivity to the amorphous carbon hard mask to reach the bottom of the structure. This is an area where engineers should look for significant material modifications, or even a new material, to help overcome these challenges.

Additionally, as multilayer stack heights increase, so does the difficulty in achieving consistent etch and deposition profiles at the top and the bottom of the memory array. For example, given a ratio of ~100:1, the selective removal of Si3N4 in the memory stack becomes a wet-etch challenge. The difficulty is removing the Si3N4 consistently at the top and bottom of the stack and across the wafer, without etching any of the SiO2. Below 96 layers, this task is performed using hot phosphoric acid (~160°C); however, at 96 layers and above, a specially formulated wet etch chemistry is needed to improve process margin.

Eliminate the slowdown

As the stack gets taller, the silicon channels extends longer, and the speed of the device becomes limited by the mobility of electrons travelling through the channels. Germanium doping (currently in development) is one known method for improving electron mobility, and suppliers are working to find even more efficient means of providing germanium dopants for 3D NAND.

The requirement is to achieve uniform doping along an HAR silicon channel approximately 50 nm in diameter and several microns deep. A promising approach may be to replace the current practice of supplying germane (GeH4) gas diluted in hydrogen with a process that uses pure germane. The objective is to look for the best option to maximize the conductivity of the channel and preserve the operational speed of the device.

The purpose of the stair structure in 3D NAND is to provide access to cells at the bottom of the NAND stack thereby allowing the deposition of tungsten (W) to form the word-lines that allow access to the cell control gates from the outside peripheral circuitry. There is one step for every layer of cells, and as more cells are stacked, the staircase gets longer. Increasingly long lengths of conductor are needed to run the length of the staircase (top to bottom, on the order of 10 μm), which in turn introduces higher resistance that affects device performance.

To address conductivity issues as the stack increases in height, it may be necessary to apply alternative metals to tungsten, which is the current standard. Chemical elements such as cobalt, ruthenium, or molybdenum have lower resistivity and better reliability at thin dimensions and could become essential to maintaining overall device performance. The challenge is developing high performance precursors that can deposit these metal films in Atomic Layer Deposition mode.

Establish defect controls early in the supply chain

As the number of memory cells increase in a 3D stack, a defect in a single cell could affect the performance of the entire cell string and hence the device. As a result, all potential contamination areas must be identified and proper steps taken to avoid any and all imperfections. Those steps range from raw materials, to synthesis of chemistries, handling of chemistries, and finally dispensing to the wafer.

For example, the presence of particulates in one cell can effectively kill an entire cell string. Also, metallic contamination (e.g. Fe, Cr, etc. from stainless steel) can destroy the cell electrical properties if they find their way to the cell layers. Likewise, large quantities of plasma etch byproducts from billions of HAR channel holes can adsorb into wafer carrier equipment and later evolve causing defects on the wafer structure. Innovations in wafer carriers (FOUPs) are required to counteract this effect. Lastly, photosensitive masking material (Photoresist), which is required at high viscosity to pattern such HAR features, is prone to bubble formation that leads to patterning defects. Innovations in combined pumping, filtration and dispensing are made to avoid such bubble formation.

Every generation of 3D NAND is becoming more sensitive to contamination, as with shrinking geometries in general, so material purity is critical. Without adequate filtration and purification, process requirements that enable increased layers and dimension shrinkage for advanced chip development cannot be achieved.

Closer collaborations between integrated device manufacturers, original equipment manufacturers, and materials makers/contamination experts across the supply chain will allow process innovations that continue to enable 3D NAND into the foreseeable future. With vertical cell stacking architecture clearly moving toward 128, 256, and perhaps beyond, the industry will achieve higher-performing, more reliable devices with greater capacity and lower cost per bit.