To address the broader range of power, performance, and area (PPA) demands of embedded applications, Synopsys, Inc. announced it has expanded its DesignWare ARC Processor IP portfolio with new 128-bit ARC VPX2 and 256-bit ARC VPX3 DSP Processors. Based on the same VLIW/SIMD architecture as the company’s higher-performance 512-bit ARC VPX5 DSP processor, the new additions deliver up to two-thirds lower power and area. The ARC VPX DSP IP family now provides greater flexibility for designers to optimize their designs based on the unique power, performance, and area (PPA) requirements of embedded workloads such as IoT sensor fusion, radar and LiDAR processing, engine control, voice/speech recognition, natural language processing, and other edge AI applications.
The smaller vector-length ARC VPX2 and VPX3 DSP processors, optimized for highly parallel processing with minimal energy and area consumption, are available in single- or dual-core configurations to address a broad range of application requirements. Each VPX core contains a scalar execution unit and multiple vector units that support 8-bit, 16-bit, and 32-bit SIMD computations. The VPX DSPs support half-, single-, and double-precision floating-point formats, and up to three floating-point pipelines are available in each VPX core. The unique hardware acceleration for special math functions used in linear and non-linear algebra functions delivers high-precision results. The new VPX DSPs include enhancements to the instruction set architecture (ISA) and load/store bandwidth to deliver up to twice the performance of existing offerings for common DSP functions such as fast Fourier transforms (FFTs). In addition, the safety-enhanced ARC VPX2FS and VPX3FS integrate hardware safety features including error correction code (ECC) protection for memories and interfaces, safety monitors, and lockstep mechanisms that help designers achieve the most stringent levels of ISO 26262 ASIL B, ASIL C, and ASIL D functional safety compliance.
Like all Synopsys ARC processors, the VPX2 and VPX3 processors are supported by the Synopsys ARC MetaWare Development Toolkit, which provides a vector length-agnostic software programming model specifically optimized for the VPX hardware architecture. The MetaWare compiler’s auto-vectorization feature transforms sequential code into vector operations for maximum throughput. Together with a robust set of software libraries that include DSP, machine learning, and linear algebra functions, the MetaWare Development Toolkit delivers a comprehensive programming environment that accelerates time to optimum results and simplifies software portability.
The broad Synopsys DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development, and integration of IP into SoCs, the company’s IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys’ extensive investment in IP quality and comprehensive technical support enables designers to reduce integration risk and accelerate time-to-market.
The Synopsys DesignWare ARC VPX2 and VPX3 DSP Processor IP are scheduled to be available to lead customers in calendar Q4 2021. The Synopsys DesignWare ARC VPX2FS and VPX3FS Processor IP are scheduled to be available to lead customers in calendar Q1 2022.