Ambiq has released a new System-on-Chip (SoC) series with three variants designed for edge computing applications. The Apollo330 Plus series implements an Arm Cortex-M55 application processor operating at speeds up to 250 MHz alongside subthreshold power optimization technology for reduced power consumption in healthcare, smart building, and industrial edge applications.
The technical architecture centers on the Arm Cortex-M55 processor with Helium technology for vector processing, capable of executing eight multiply-accumulate operations per cycle. The memory configuration includes 2MB of on-chip system RAM, 2MB of embedded non-volatile memory, 32kB instruction cache, and 32kB data cache connected via a wide bus architecture. The system integrates a digital microphone PDM interface for audio input processing at low power states.
The three variants in the series include differentiated wireless connectivity options. The base model provides peripheral interfaces without wireless connectivity for wired applications in medical devices and sensor-based systems. The second variant adds Bluetooth Low Energy connectivity for wireless peripheral connections and audio applications. The third variant implements a multi-protocol radio supporting IEEE 802.15.4, Thread, and Matter protocols with transmission power up to +14dBm.
The multi-core architecture implements a dual-processor design with the primary Arm Cortex-M55 application processor handling computational tasks while a secondary 48/96 MHz Arm Cortex-M4F serves as a network processor in the wireless variants. This separation of processing functions maintains radio performance during computationally intensive operations.
Security functionality includes hardware-based mechanisms built on Arm TrustZone technology. The implementation provides secure boot capabilities, encrypted firmware update mechanisms, and memory protection to prevent unauthorized access to sensitive data. These hardware security features are accessible through a security API for application integration.
The power management system incorporates subthreshold voltage operation to reduce energy consumption during both active and sleep states. This technical approach enables the processor to operate at lower voltages while maintaining functionality, extending battery life in portable applications. Vector processing optimizations for AI operations reduce computation time and associated power consumption when executing neural network models.
The chip family supports multiple package options for integration into space-constrained devices. Interface options include I2C, SPI, UART, I2S, PDM, and GPIO with configurable interrupt capabilities. Additional peripheral interfaces accommodate various sensor types and external memory expansion.
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