• Skip to primary navigation
  • Skip to main content
  • Skip to primary sidebar
  • Skip to footer

Microcontroller Tips

Microcontroller engineering resources, new microcontroller products and electronics engineering news

  • Products
    • 8-bit
    • 16-bit
    • 32-bit
    • 64-bit
  • Applications
    • 5G
    • Automotive
    • Connectivity
    • Consumer Electronics
    • EV Engineering
    • Industrial
    • IoT
    • Medical
    • Security
    • Telecommunications
    • Wearables
    • Wireless
  • Learn
    • eBooks / Tech Tips
    • EE Training Days
    • FAQs
    • Learning Center
    • Tech Toolboxes
    • Webinars/Digital Events
  • Resources
    • Design Guide Library
    • LEAP Awards
    • Podcasts
    • White Papers
  • Videos
    • EE Videos & Interviews
    • Teardown Videos
  • EE Forums
    • EDABoard.com
    • Electro-Tech-Online.com
  • Engineering Training Days
  • Advertise
  • Subscribe

Energy processing unit accelerates design of SoC power management

May 12, 2016 By Abby Esposito Leave a Comment

sonics logoSonics, Inc. has announced that it has developed the IP industry’s first Energy Processing Unit (EPU) based on the company’s ICE-Grain (Instant Control of Energy) Power Architecture originally introduced in 2015. Sonics’ ICE-G1 product is a complete EPU enabling rapid design of system-on-chip (SoC) power architecture and implementation and verification of the resulting power management subsystem. Sonics also announced the “Energy Processing for Power-Sensitive SoCs” seminar series which highlights power savings results from real-world customer use cases.

About EPUs
No amount of wasted energy is affordable in today’s electronic products. Designers know that their circuits are idle a significant fraction of time, but have no proven technology that exploits idle moments to save power. An EPU is a hardware subsystem that enables designers to better manage and control circuit idle time. Where the host processor (CPU) optimizes the active moments of the SoC components, the EPU optimizes the idle moments of the SoC components. By construction, an EPU delivers lower power consumption than software-controlled power management. EPUs possess the following characteristics:

Fine-grained power partitioning maximizes SoC energy savings opportunities
Autonomous hardware-based control provides orders of magnitude faster power up and power down than software-based control through a conventional processor
Aggregation of architectural power savings techniques ensures minimum energy consumption
Reprogrammable architecture supports optimization under varying operating conditions and enables observation-driven adaptation to the end system.

About ICE-G1
The Sonics’ ICE-G1 EPU accelerates the development of power-sensitive SoC designs using configurable IP and an automated methodology, which produces EPUs and operating results that improve upon the custom approach employed by expert power design teams. As the industry’s first licensable EPU, ICE-G1 makes sophisticated power savings techniques accessible to all SoC designers in a complete subsystem solution. Using ICE-G1, experienced and first-time SoC designers alike can achieve significant power savings in their designs.

ICE-G1 is currently available on a limited basis to qualified customers. ICE-G1 works with all internal and third-party IP offerings from processors to I/Os to NoCs. Combining the ICE-G1 EPU with the SonicsGN NoC simplifies fine-grained power management for SoC integration teams.
Markets for ICE-G1 include:

• Application and Baseband Processors
• Tablets, Notebooks
• IoT
• Datacenters
• EnergyStar compliant systems
• Form factor constrained systems—handheld, battery operated, sealed case/no fan, wearable.

ICE-G1 key product features are:

Intelligent event and switching controllers–power grain controllers, event matrix, interrupt controller, software register interface—configurable and programmable hardware that dynamically manages both active and leakage power.

SonicsStudio SoC development environment—graphical user interface (GUI), power grain identification (import IEEE-1801 UPF, import RTL, described directly), power architecture definition, power grain controller configuration (power modes and transition events), RTL and UPF code generation, and automated verification test bench generation tools. A single environment that streamlines the EPU development process from architectural specification to physical implementation.

Automated SoC power design methodology integrated with standard EDA functional and physical tool flows (top down and bottom up)—abstracts the complete set of power management techniques and automatically generates EPUs to enable architectural exploration and continuous iteration as the SoC design evolves.

Technical support and consulting services—including training, energy savings assessments, architectural recommendations, and implementation guidance.

About the Seminar Series

The “Energy Processing for Power-Sensitive SoCs” seminar series agenda covers:
Why power management is a MUST HAVE capability to successfully address power-sensitive application and market requirements
Fundamentals of SOC power management
Defining characteristics of an EPU
Power savings results from real-world examples
EPU for widely available, commercial 4K video decoder
EPU for sensor designs without a host processor
ICE-G1 technology overview and demonstration.

Seminar locations:

Silicon Valley
Wednesday, May 25th, 11:00 am – 1:00 pm
Santa Clara Hyatt Regency, 5101 Great America Parkway
Mendocino Room (second floor)

Austin, Texas
Monday, June 6th, 11:00 am – 1:00 pm
Austin Hilton (DAC HQ), 500 East 4th Street
Meeting room 408, (fourth floor)

Sonics
sonicsinc.com

Filed Under: Products Tagged With: sonics

Reader Interactions

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Primary Sidebar

Featured Contributions

Can chiplets save the semiconductor supply chain?

Navigating the EU Cyber Resilience Act: a manufacturer’s perspective

The intelligent Edge: powering next-gen Edge AI applications

Engineering harmony: solving the multiprotocol puzzle in IoT device design

What’s slowing down Edge AI? It’s not compute, it’s data movement

More Featured Contributions

EE TECH TOOLBOX

“ee
Tech Toolbox: Connectivity
AI and high-performance computing demand interconnects that can handle massive data throughput without bottlenecks. This Tech Toolbox explores the connector technologies enabling ML systems, from high-speed board-to-board and PCIe interfaces to in-package optical interconnects and twin-axial assemblies.

EE Learning Center

EE Learning Center

EE ENGINEERING TRAINING DAYS

engineering
“bills
“microcontroller
EXPAND YOUR KNOWLEDGE AND STAY CONNECTED
Get the latest info on technologies, tools and strategies for EE professionals.

Footer

Microcontroller Tips

EE World Online Network

  • 5G Technology World
  • EE World Online
  • Engineers Garage
  • Analog IC Tips
  • Battery Power Tips
  • Connector Tips
  • EDA Board Forums
  • Electro Tech Online Forums
  • EV Engineering
  • Power Electronic Tips
  • Sensor Tips
  • Test and Measurement Tips

Microcontroller Tips

  • Subscribe to our newsletter
  • Advertise with us
  • Contact us
  • About us

Copyright © 2026 · WTWH Media LLC and its licensors. All rights reserved.
The material on this site may not be reproduced, distributed, transmitted, cached or otherwise used, except with the prior written permission of WTWH Media.

Privacy Policy