The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor’s Catapult HLS and Achronix’s ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve quality of results (QoR), it is suitable for any design targeting Achronix technology.
The Catapult HLS to Speedcore embedded FPGA technology flow gives designers the ability to make algorithmic changes in late stages of IP development and to optimize the algorithm and the digital micro-architecture. The integrated verification environment allows reuse of the software tests for generated register transfer level (RTL) code, reducing the need for dedicated RTL test benches by more than 80 percent.
Achronix ACE design tools support Catapult’s RTL constructs and primitives. Currently Achronix libraries for its Speedcore eFPGA products and for its Speedster standalone FPGAs are integrated into the flow.
The Achronix high-performance and high-density FPGA technology can be used for diverse hardware acceleration applications in data center compute, networking and storage; 5G wireless infrastructure, network acceleration; advanced driver assistance systems (ADAS) and autonomous vehicles.
Early versions of the design and development environment are available now.