CEVA, Inc. announced today CEVA-BX, its new all-purpose, hybrid DSP / Controller architecture to address new algorithms of digital signal processing in voice, video, communication, sensing and digital signal control applications. Offering general purpose DSP capabilities required for motor control and electrification, the CEVA-BX architecture extends CEVA’s market reach into the burgeoning automotive and industrial markets currently underserved by legacy DSPs or MPU/MCUs with low performance DSP co-processing.
CEVA-BX offers a new breed of DSP architecture, combining the inherent low power requirements of DSP kernels with the high-level programming and compact code size requirements of a large control code base. Using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at TSMC 7nm process node using common standard cells and memory compilers. The CEVA-BX Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) widely used in neural network inference, noise reduction and echo cancellation, as well as half, single and double precision floating point units for high accuracy sensor fusion and positioning algorithms.
Mike Demler, Senior Analyst at The Linley Group commented: “Consumer, automotive, industrial and healthcare devices are increasingly integrating multiple sensors, such as cameras, microphones, environmental and motion detectors, which produce data that must be fused, interpreted, and processed on-device before being sent via a wireless link to the cloud. Processing these heavy-duty signal-processing workloads in edge devices requires an efficient combination of control and DSP capabilities. The CEVA-BX eliminates the need for separate CPUs and DSP coprocessors, employing a hybrid architecture that delivers excellent all-round performance for smart devices.”
CEVA-BX employs key architecture principles of advanced micro-processor architectures such as a large orthogonal general purpose register set for maximum C compiler efficiency, innovative Branch Target Buffer (BTB) for minimizing branch overhead, hardware loop buffer for reduced power consumption of code loops, fully cached memory subsystem, and native support for all standard C types. Its CoreMark/MHz score of 4.5 reflects the superior control capabilities of the architecture. CEVA-BX customers are able to add proprietary ISA into the architecture using the CEVA-Xtend, to accelerate proprietary algorithms and take advantage of CEVA’s automatic Queue and Buffer management mechanisms to integrate co-processors and create a cluster of CEVA-BX cores.
The CEVA-BX is initially offered in two configurations – the CEVA-BX1 with single 32X32-bit MAC and quad 16X16-bit MACs and the CEVA-BX2 with quad 32X32-bit MACs and octal 16X16-bit MACs, that are also capable of supporting 16×8-bit and 8×8-bit MAC operations. The CEVA-BX2 addresses intensive workloads such as 5G PHY control, multi-microphone beamforming and neural networks for speech recognition, with up to 16 GMACs per second. The CEVA-BX1 serves low to mid-range DSP workloads, such as cellular IoT, protocol stacks, and always-on sensor fusion, with up to 8 GMACs per second. Security is addressed using dedicated trusted execution modes to comply with the stringent safety standards.
The CEVA-BX cores are available now to lead customers and by end of Q1/2019 for general licensing.