Synopsys announced immediate availability of the latest release of its flagship IC Compiler II place-and-route system that includes several new innovative technologies to deliver superior quality-of-results (QoR) and fastest time-to-results (TTR) for the next wave of leading-edge designs across a wide range of vertical markets, including automotive, cloud computing, AI, networking and wireless applications.
Continued investment in technology advancements in IC Compiler II technologies deliver ten percent total power reduction, five percent smaller area, five percent better timing, and 2X faster runtime. Based on observed benefits, Realtek has deployed the latest IC Compiler II technologies on their next-generation communication network designs to meet stringent power, performance, and area (PPA) budgets while speeding up TTR for their designs.
Key new technologies in IC Compiler II for superior QoR include a common physical optimization infrastructure, new arc-based unified concurrent clock-and-data (CCD) optimization, physically-aware logic re-synthesis, and dynamic voltage drop-driven power shaping. RedHawk Analysis Fusion IR drop-driven optimization, exhaustive path-based analysis (PBA), and signoff accuracy within IC Compiler II result in unmatched design convergence. Several new speed-up improvements, including inherent core engine algorithm speed-up, intelligent scenario management, efficient hardware scaling, and flow concurrency, deliver 2X faster design throughput.