Logic simulator adds machine learning to speed verification tasks

Cadence Design Systems, Inc. announced that the Cadence Xcelium Logic Simulator has been enhanced with machine learning technology (ML), called Xcelium ML, to increase verification throughput. Using new machine learning technology and core computational software, Xcelium ML enables up to 5X faster verification closure on randomized regressions.

Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium ML learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles.

Cadence’s Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments.

Xcelium ML is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.