MIPI C-PHY/D-PHY combo speeds development of high-bandwidth displays

Mixel, Inc. announced a state-of-the-art solution for next-generation displays. This integrated solution brings together the IP of the three MIPI Alliance member companies enabling rapid deployment of mobile, AR/VR, and automotive displays leveraging MIPI DSI-2 technology. This optimized solution is available immediately and includes:

Targeting display applications requiring high bandwidth and excellent power efficiency, this subsystem solution brings a significant improvement in overall throughput available with DSI-2. This level of integration using proven, broadly adopted IP sets a new benchmark for performance, ease of implementation, and time to market.

Benefits of the Mixel-Rambus-Hardent MIPI DSI-2 Solution include: Optimized for ASIC design performance (PPA); Maximized functionality and availability of all MIPI DSI-2 operating modes; Lower project risk with a fully integrated and verified IP solution; Accelerate ASIC and SoC time to market

Mixel’s MIPI C-PHY/D-PHY combo IP is a high-frequency, low-power, low-cost, physical layer. It can be configured as a MIPI transmitter or receiver, supporting both the camera interface MIPI CSI-2 v3.0 and display interface DSI-2 v1.1 and is backward compatible with previous generations of each specification. In C-PHY mode, Mixel’s MIPI C-PHY v2.0 supports a speed of 4.5 giga-symbols per second (Gsps) per trio which is an equivalent data rate of 10.26 Gbps/trio. In D-PHY mode, the IP supports speeds up to 4.5 Gbps per lane and complies with the MIPI D-PHY v2.5 specification. With up to three trios in C-PHY and up to four lanes in the D-PHY, the combo IP reaches an aggregate bandwidth of 30.78 Gbps and 18 Gbps in their respective modes.

The Rambus DSI-2 Controller cores are DSI-2 v1.1 compliant and optimized for high performance, low power, and small size. The cores are full-featured supporting host (Tx) and peripheral (Rx), multiple user interface options, and are highly configurable. 64 and 32-bit core widths are available enabling the user to make clock rate versus size tradeoffs.

Hardent’s VESA Display Stream Compression (DSC) IP cores are designed for use in cutting-edge display applications where visually lossless, ultra-low latency compression is required. DSC video compression increases overall transmission bandwidth on the MIPI DSI-2 transport interface by up to 3X, allowing designers to free up the bandwidth needed to create displays with higher resolutions, faster refresh rates, and greater color depths.

The Mixel, Rambus, and Hardent MIPI DSI-2 / VESA DSC subsystem solution are available in both host (TX) and peripheral (RX) versions.