• Skip to primary navigation
  • Skip to main content
  • Skip to primary sidebar
  • Skip to footer

Microcontroller Tips

Microcontroller engineering resources, new microcontroller products and electronics engineering news

  • Products
    • 8-bit
    • 16-bit
    • 32-bit
    • 64-bit
  • Applications
    • Automotive
    • Connectivity
    • Consumer Electronics
    • Industrial
    • Medical
    • Security
  • EE Forums
    • EDABoard.com
    • Electro-Tech-Online.com
  • Videos
    • TI Microcontroller Videos
  • EE Resources
    • DesignFast
    • eBooks / Tech Tips
    • FAQs
    • LEAP Awards
    • Podcasts
    • Webinars
    • White Papers
  • EE Learning Center

New IDE linker program shrinks executable code by 15%

December 11, 2020 By Redding Traiger Leave a Comment

SEGGER’s Embedded Studio for RISC-V now comes with the SEGGER Linker in addition to the GNU linker. The SEGGER Linker has been developed from the ground up to create executables for Embedded Systems.

For RISC-V, it shrinks the size of the resulting programs by up to 15%, shortens link time, delivers a detailed map file, and provides more flexibility.

Based on the same code as the SEGGER Linker for ARM, which is well-proven in SEGGER’s leading integrated development environment “Embedded Studio for ARM”, it inherited a lot of noteworthy features, such as integrated integrity check generation with a number of algorithms (CRCs and hashes), the ability to automatically place code and data in non-contiguous regions, and prioritize data into fast memories.

To achieve this improvement in code density, the new RISC-V linker uses a combination of various optimization strategies. Such techniques include ordering code and data in the most efficient way to use short addressing modes, as well as replacing code sequences with more efficient ones, along with the use of spring-boarding technologies.

You may also like:

  • RISC-V
    Growing availability of tools reducing risk of using RISC-V
  • RiSC-V
    RISC-V is growing and offers stability, scalability and security

  • What is the HART protocol?

  • Security for embedded systems – Virtual Roundtable (part 1 of…
  • RISC-V
    RISC-V: an Open Instruction Set Architecture

Filed Under: Applications, Embedded, RISC-V, Software, Tools Tagged With: segger

Reader Interactions

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Primary Sidebar

DesignFast

Component Selection Made Simple.

Try it Today
design fast globle

EE Training Center Classrooms

“ee

“ee

“ee

“ee

“ee

Subscribe to our Newsletter

Subscribe to weekly industry news, new product innovations and more.

Subscribe today

RSS Current EDABoard.com discussions

  • CMOS inverter basic questions
  • usb info
  • LR8 linear regulator running off 510V when 480V is abs max?
  • Whirlpool washing machine l1961
  • ESL of ceramic capacitor seems too high, at 8.8uH

RSS Current Electro-Tech-Online.com Discussions

  • Question PS2 slim 90000 components
  • Keep battery hot
  • laptop car charger
  • Sampling an AC signal
  • Tesla coil progress

Follow us on Twitter

Tweets by MicroContrlTips

Footer

Microcontroller Tips

EE World Online Network

  • DesignFast
  • EE World Online
  • EDA Board Forums
  • Electro Tech Online Forums
  • Connector Tips
  • Analog IC Tips
  • Power Electronic Tips
  • Sensor Tips
  • Test and Measurement Tips
  • Wire and Cable Tips
  • 5G Technology World

Microcontroller Tips

  • Subscribe to our newsletter
  • Advertise with us
  • Contact us
  • About us
Follow us on TwitterAdd us on FacebookFollow us on YouTube Follow us on Instagram

Copyright © 2021 · WTWH Media LLC and its licensors. All rights reserved.
The material on this site may not be reproduced, distributed, transmitted, cached or otherwise used, except with the prior written permission of WTWH Media.

Privacy Policy