Microchip Technology introduced its Switchtec Gen 6 PCIe switches, manufactured using a 3 nm process. The switches support PCIe 6.0 specifications with up to 160 lanes for AI system connectivity and feature a hardware root of trust with post-quantum safe cryptography compliant with Commercial National Security Algorithm Suite 2.0.
PCIe 6.0 delivers 64 GT/s per lane, doubling the bandwidth of PCIe 5.0. The specification introduces Flow Control Unit mode, Forward Error Correction, and dynamic resource allocation to improve data transfer efficiency and reliability for small packets common in AI workloads. These features address bandwidth bottlenecks that occur when data transfers between CPUs, GPUs, memory, and storage devices.
Switchtec Gen 6 switches enable high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators, and storage devices in data center environments. The switches feature 20 ports and 10 stacks with hot-plug and surprise-plug controllers on each port. The design supports Non-Transparent Bridging to connect and isolate multiple host domains and multicast for one-to-many data distribution within a single domain.
The switches include error containment features, diagnostics and debug capabilities, and an integrated MIPS processor with bifurcation options at x8 and x16. Input and output reference clocks are based on PCIe stacks with four input clocks per stack.
Microchip’s ChipLink diagnostic tools support the Switchtec Gen 6 family with debug, diagnostics, configuration and analysis through a graphical user interface. ChipLink connects via in-band PCIe or sideband signals, including UART, TWI, and EJTAG for monitoring and troubleshooting during design and deployment. The PM61160-KIT Switchtec Gen 6 PCIe Switch Evaluation Kit provides multiple interfaces for testing.
Switchtec Gen 6 PCIe switches are available for sampling to qualified customers through Microchip sales representatives or authorized distributors.
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