Physically aware RTL design system halves SoC implementation cycle

Synopsys announced the immediate availability of RTL Architect, an innovative product that signifies a shift-left for RTL design closure. Synopsys RTL Architect is the industry’s first physically aware RTL design system, which reduces the SoC implementation cycle in half and delivers superior quality-of-results (QoR).

RTL teams are increasingly faced with the challenges of rapidly exploring domain-specific RTL architectures to achieve significant power, performance and area (PPA) gains to meet the requirements of new market verticals like artificial intelligence and automotive applications. Existing point tool solutions for estimating RTL quality are severely limited due to poor accuracy to downstream implementation. These early design cycle inaccuracies cause downstream implementation tools to compensate, often having to go back and make RTL changes to meet the PPA goals. RTL Architect addresses these challenges utilizing a rapid multi-objective prediction engine derived from the Synopsys Fusion Design Platform implementation environment to predict PPA of downstream implementation accurately. RTL Architect enables RTL designers to pinpoint bottlenecks in their source code to improve RTL quality.

The RTL Architect system is built on a unified data model that provides multi-billion gate capacity and comprehensive hierarchical design capabilities to accommodate the growing design and block sizes at advanced process nodes. It directly leverages Synopsys’ world-class implementation and golden signoff solutions to deliver results that are accurate early in the design cycle and correlate-by-construction.

RTL Architect uses a fast, multi-dimensional implementation prediction engine that enables RTL designers to predict the power, performance, area, and congestion impact of their RTL changes. Synopsys’ PrimePower golden signoff power analysis engine is directly integrated for accurate RTL power estimation and optimization for energy-efficient designs. RTL Architect provides a unified workflow environment for simplified ease-of-use and seamless analysis of key PPA quality metrics. For existing users of PrimePower at the gate-level, PrimePower RTL power estimation is also available, enabling a consistent RTL to signoff power analysis flow.