Microchip Technology has launched the first devices in its planned family of PIC64 High-Performance Spaceflight Computing (PIC64-HPSC) microprocessors (MPUs) to support the diverse and growing global space market’s expanding computational needs, including more autonomous applications. The radiation- and fault-tolerant PIC64-HPSC MPUs, delivered to NASA and the broader defense and commercial aerospace industry, integrate widely adopted RISC-V CPUs with vector-processing instruction extensions to support Artificial Intelligence/Machine Learning (AI/ML) applications. These MPUs also feature a suite of industry-standard interfaces and protocols not previously available for space applications. An ecosystem of partners is being assembled to expedite the development of integrated system-level solutions, featuring Single-Board Computers (SBCs), space-grade companion components, and a network of open-source and commercial software partners.

The Radiation-Hardened (RH) PIC64-HPSC RH is designed to provide autonomous missions with the local processing power needed to execute real-time tasks such as rover hazard avoidance on the Moon’s surface, while also enabling long-duration, deep-space missions like Mars expeditions, requiring extremely low-power consumption and the ability to withstand harsh space conditions. For the commercial space sector, the Radiation-Tolerant (RT) PIC64-HPSC RT is designed to meet the needs of Low Earth Orbit (LEO) constellations, where system providers must prioritize low cost over longevity, while ensuring high fault tolerance for reliable round-the-clock service and cybersecurity of space assets.

PIC64-HPSC MPUs offer various capabilities, including a space-grade 64-bit MPU architecture with eight SiFive RISC-V X280 64-bit CPU cores supporting virtualization and real-time operation, and vector extensions that can deliver up to 2 TOPS (int8) or 1 TFLOPS (bfloat16) of vector performance for AI/ML processing. They include high-speed network connectivity with a 240 Gbps Time Sensitive Networking (TSN) Ethernet switch for 10 GbE connectivity, scalable and extensible PCIe Gen 3 and Compute Express Link (CXL) 2.0, and RMAP-compatible SpaceWire ports with internal routers. The MPUs facilitate low-latency data transfers from remote sensors using Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCEv2) hardware accelerators, maximizing compute capabilities. They implement platform-level defense-grade security with support for post-quantum cryptography and anti-tamper features, and support high fault-tolerance capabilities with Dual-Core Lockstep (DCLS) operation, WorldGuard hardware architecture, and an on-board system controller for fault monitoring and mitigation. Additionally, they include dynamic controls for flexible power tuning to balance computational demands during various phases of space missions with tailored activation of functions and interfaces.