• Skip to primary navigation
  • Skip to main content
  • Skip to primary sidebar
  • Skip to footer

Microcontroller Tips

Microcontroller engineering resources, new microcontroller products and electronics engineering news

  • Products
    • 8-bit
    • 16-bit
    • 32-bit
    • 64-bit
  • Applications
    • Automotive
    • Connectivity
    • Consumer Electronics
    • Industrial
    • Medical
    • Security
  • EE Forums
    • EDABoard.com
    • Electro-Tech-Online.com
  • Videos
    • TI Microcontroller Videos
  • EE Resources
    • DesignFast
    • eBooks / Tech Tips
    • FAQs
    • LEAP Awards
    • Podcasts
    • Webinars
    • White Papers
  • EE Learning Center

RISC vs. CISC Architectures: Which one is better?

January 9, 2018 By Scott Thornton 7 Comments

Reduced Instruction Set Computer (RISC) is a type or category of the processor, or Instruction Set Architecture (ISA).  Speaking broadly, an ISA is a medium whereby a processor communicates with the human programmer (although there are several other formally identified layers in between the processor and the programmer). An instruction is a command given to the processor to perform an action. An instruction set is the entire collection of instructions for a given processor, and the term architecture implies a particular way of building the system that makes the processor.

RISC generally refers to a streamlined version of its predecessor, the Complex Instruction Set Computer (CISC). At the dawn of processors, there was no formal identification known as CISC, but the term has since been coined to identify them as different from the RISC architecture. Some examples of CISC microprocessor instruction set architectures (ISAs) include the Motorola 68000 (68K), the DEC VAX, PDP-11, several generations of the Intel x86, and 8051.

Examples of processors with the RISC architecture include MIPS, PowerPC, Atmel’s AVR, the Microchip PIC processors, Arm processors, RISC-V, and all modern microprocessors have at least some elements of RISC. The progression from 8- and 16-bit to 32-bit architectures essentially forced the need for RISC architectures. Nevertheless, it took a decade before RISC architectures began to take hold, mainly due to lack of software that would run on RISC architectures. Intel also made an impact, since it had the means to continue using the CISC architecture and found no need to redesign from the ground up. The MIPS architecture was one of the first RISC ISAs and has been used widely to teach the RISC architecture.

Some history
The first integrated chip was designed in 1958 by Jack Kilby. Microprocessors were introduced in the 1970s, the first commercial one coming from Intel Corporation. By the early 1980s, the RISC architecture had been introduced. The RISC design came about as a total redesign because the CISC architecture was becoming more complex. Most credit John Cocke of IBM as having come up with the RISC concept. History tells us that to get a faster computer, some major changes in the microprocessor architecture took place that became RISC, including a uniform format for instructions and easily pipelined instructions. (Pipelining means the processor starts to execute the next instruction before the present instruction is completed.) In the 1970s, memory was costly, so smaller programs were a focus.

What are the differences between RISC and CISC?
The short answer is that RISC is perceived by many as an improvement over CISC. There is no best architecture since different architectures can simply be better in some scenarios but less ideal in others.  RISC-based machines execute one instruction per clock cycle. CISC machines can have special instructions as well as instructions that take more than one cycle to execute. This means that the same instruction executed on a CISC architecture might take several instructions to execute on a RISC machine. The RISC architecture will need more working (RAM) memory than CISC to hold values as it loads each instruction, acts upon it, then loads the next one.

The CISC architecture can execute one, albeit more complex instruction, that does the same operations, all at once, directly upon memory. Thus, RISC architecture requires more RAM but always executes one instruction per clock cycle for predictable processing, which is good for pipelining. One of the major differences between RISC and CISC is that RISC emphasizes efficiency in cycles per instruction and CISC emphasizes efficiency in instructions per program. A fast processor is dependent upon how much time it takes to execute each clock cycle, how many cycles it takes to execute instructions, and the number of instructions there are in each program. RISC has an emphasis on larger program code sizes (due to a smaller instruction set, so multiple steps done in succession may equate to one step in CISC).

The RISC ISA emphasizes software over hardware. The RISC instruction set requires one to write more efficient software (e.g., compilers or code) with fewer instructions. CISC ISAs use more transistors in the hardware to implement more instructions and more complex instructions as well.

RISC needs more RAM, whereas CISC has an emphasis on smaller code size and uses less RAM overall than RISC. Many microprocessors today hold a mix of RISC- and CISC-like attributes, however, such as a CISC-like ISA that treats instructions as if they are a string of RISC-type instructions.

Some major differences between CISC and RISC architectures are listed in Table 1.

RISC vs. CISC
Table 1: Table of some of the differences between CISC and RISC Instruction Set Architectures (ISAs).

 

You may also like:


  • RISC-V ecosystem surpasses 100 members globally

  • Webinar: The RISC-V ecosystem is ready for prime time. Get…

  • RISC architecture and instruction architecture

Filed Under: Embedded, FAQ, Featured, RISC-V Tagged With: basics, FAQ

Reader Interactions

Comments

  1. Salman says

    May 25, 2019 at 5:48 am

    Well Written. Thankyou

    Reply
  2. Shanthanu says

    December 10, 2019 at 2:49 am

    Good read. Was a good refresher to RISC vs CISC

    Reply
  3. TECH says

    April 2, 2020 at 9:13 am

    Very well written and informative!

    Reply
  4. jonathan says

    December 5, 2020 at 5:13 am

    Nice writeup

    Reply

Trackbacks

  1. Computer architecture revisited – DevOut says:
    April 4, 2020 at 4:16 am

    […] https://www.microcontrollertips.com/risc-vs-cisc-architectures-one-better/ […]

    Reply
  2. Is Apple ditching Intel for ARM? Yes… and no. | GetConnected says:
    June 22, 2020 at 11:30 am

    […] were powered by PowerPC chips. PowerPC was a joint operation between Motorola and IBM, a Reduced Instruction Set Computing processor – or RISC chip. Back then, the speed and power of the PowerPC banked on it being able to […]

    Reply
  3. Apple Pivots – WWDC 2020 « digitalfilms says:
    June 28, 2020 at 11:49 am

    […] Apple Silicon becomes the third processor transition for the Mac. Apple has been using Intel CPUs for 15 years. This shift moves Mac computers to the same CPU family as the mobile platforms. The new CPUs are based on Arm SoC (system on chip) technology. Arm originally stood for Acorn RISC Machine and is a technology developed by Arm Holdings PLC. They license the technology to other companies who are then free to develop their own chip designs. As far as we know, the Apple Arm chips will be manufactured in foundries owned by TSMC in Taiwan. While any hardware shift can be disconcerting, the good news is that Apple already has more than a decade-long track record with these chips, thanks to the iPhone and iPad. (Click here for more details on RISC versus CISC chip architectures.) […]

    Reply

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Primary Sidebar

DesignFast

Component Selection Made Simple.

Try it Today
design fast globle

EE Training Center Classrooms

“ee

“ee

“ee

“ee

Subscribe to our Newsletter

Subscribe to weekly industry news, new product innovations and more.

Subscribe today

RSS Current EDABoard.com discussions

  • cmos leakage and average current
  • PSoC1 programming
  • Kitchen balance load cells 10 kg
  • CLOCK DIVIDER
  • dsPIC33f ADC reading voltage help

RSS Current Electro-Tech-Online.com Discussions

  • infrasonic frequency
  • Definitive Technology Subwoofer repair
  • Dust extractor remote switch
  • Best way to reverse a DC motor
  • Touch circuit sound, led. 555 timer

Follow us on Twitter

Tweets by MicroContrlTips

Footer

Microcontroller Tips

EE World Online Network

  • DesignFast
  • EE World Online
  • EDA Board Forums
  • Electro Tech Online Forums
  • Connector Tips
  • Analog IC Tips
  • Power Electronic Tips
  • Sensor Tips
  • Test and Measurement Tips
  • Wire and Cable Tips
  • 5G Technology World

Microcontroller Tips

  • Subscribe to our newsletter
  • Advertise with us
  • Contact us
  • About us
Follow us on TwitterAdd us on FacebookFollow us on YouTube Follow us on Instagram

Copyright © 2021 · WTWH Media LLC and its licensors. All rights reserved.
The material on this site may not be reproduced, distributed, transmitted, cached or otherwise used, except with the prior written permission of WTWH Media.

Privacy Policy