SoC verification software delivers 5X faster design load and tracing

Synopsys announced a new release of its Verification Continuum Platform with new native integrations across verification tools, enabling up to 5X higher verification performance. Verification Continuum is built from the industry’s fastest engines developed by Synopsys, including Virtualizer™ virtual prototyping, SpyGlass static and VC Formal® verification technologies, VCS simulation, ZeBu emulation, Synopsys HAPS prototyping, Verdi debug, and VC Verification IP (VIP). Increasing system-on-chip (SoC) complexity, growing SoC software content, and rising time-to-market pressures are driving the need for a highly-efficient verification platform. New enhanced native integrations in Verification Continuum enable performance gains between all verification engines, accelerating time-to-market for complex SoC designs.

New Native Integrations

• Simulation and Debug—The new Verdi release delivers Smart Loading technology, enabled by Unified Compile with VCS, that speeds Verdi design load time by 5X. Additionally, enhanced native multi-threaded dumping cuts overhead by 50 percent, and the new dynamic waveform aliasing technology enables 3X smaller FSDB size.
• Static Verification, Simulation, and Debug—Native integration of SpyGlass and VCS Unified Compile enables seamless read of DesignWare® IP and encrypted IP designs, significantly improving ease-of-use compared to previous black-box support of IP. In addition, integration of Verdi’s Unified Debug interface with SpyGlass enables a consistent debug user experience across the verification flow.
• Formal Verification and Functional Qualification—The new VC Formal release delivers 2X performance improvement with enhanced engine optimization and orchestration. Native integration of the VC Formal testbench analyzer (FTA) application and Certitude® functional qualification system enables 10X faster quality assessment of testbench and assertions. This is achieved with a single compile and intelligent fault injection and scheduling for formal property verification.
• Simulation and Verification IP—Native integration across VCS and VC Verification IP delivers a 2X speed-up in simulation performance. This is achieved by optimizations between VCS and VC VIP leveraging native UVM technology and industry-leading constraint solver technology.
• Accelerated VIP, Emulation, and Simulation—Unified compile of design and testbench and low latency interface supporting a seamless mix of signal-level and transaction-level communication, combined with native integration of VCS, ZeBu, and Accelerated VIP, deliver 10-100X speed-up in simulation acceleration compared to simulation alone.