XMOS reveals a RISC-V-compatible architecture for the fourth generation of its xcore platform. The collaboration delivers the flexibility to define entire systems in software, enabling RISC-V programmers to rapidly realize the most differentiated and economical solutions to the intelligent IoT.
By transitioning to a RISC-V compatible architecture, more embedded system designers will have access to the technical advantages of the xcore platform, while using the tools and processes that they are most accustomed to. Existing xcore users will also benefit from the familiarity and compatibility that comes with RISC-V and its growing ecosystem.
With xcore’s dynamic flexibility delivering any combination of AI, I/O, DSP, and standard compute in a single device, those familiar with standard embedded programming and AI techniques can quickly create systems in software that would previously have required an expensive and time-consuming chip design.
The move is a significant milestone in XMOS’s wider strategy of broadening access to its technology through the use of best-in-class open-source architectures, tools, and runtime software. This already includes LLVM, GDB, TensorFlow, C/C++, FreeRTOS, and numerous third-party models.
XMOS will be further discussing the adoption of the RISC-V architecture during the RISC-V Summit in San Jose this week.