cadencedesignsystems

Logic simulator adds machine learning to speed verification tasks

August 14, 2020 By Aimee Kalnoskas Leave a Comment

Cadence Design Systems, Inc. announced that the Cadence Xcelium Logic Simulator has been enhanced with machine learning technology (ML), called Xcelium ML, to increase verification throughput. Using new machine learning technology and core computational software, Xcelium ML enables up to 5X faster verification closure on randomized regressions.

Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium ML learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles.

Cadence’s Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments.

Xcelium ML is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.

Automated security validation platform identifies vulnerabilities in firmware and SoC designs

May 30, 2019 By Aimee Kalnoskas Leave a Comment

Tortuga Logic, a cybersecurity company specializing in hardware threat detection and prevention, announced the launch of Radix-M, the industry’s first platform capable of performing security validation of firmware on complex system-on-chip (SoCs) designs. Built with funding support from the Defense Advanced Research Projects Agency (DARPA), Radix-M identifies and prevents unknown firmware vulnerabilities. It also automates previously manual processes firmware engineers and SoC security teams conduct using the existing hardware- and cloud-based Cadence Palladium Z1 Enterprise Emulation Platform for seamless hardware and software execution.

“Engineering teams spend tremendous time and effort validating their firmware and chip designs, yet the methods can sometimes pose challenges when it comes to detecting security vulnerabilities,” said Paul Cunningham, Corporate VP and GM of the Systems and Verification Group at Cadence Design Systems. “Cadence collaborated with Tortuga Logic on the development and use of Tortuga Logic’s Radix-M with our Palladium Z1 emulation platform by targeting firmware vulnerabilities in modern SoCs and reducing the risk of security exploits from reaching the field.”

SoC design teams run emulation to ensure their firmware is operating correctly. Firmware sets hardware configuration parameters to ensure correct functionality. Traditionally, the only way to assess firmware security has been through a tedious, manual process that does not adequately identify vulnerabilities directly associated with the hardware, where the majority of exploits occur. In addition, product engineers largely rely on parameters set by security architects to secure their configurations, often resulting in a disconnect between the two teams that allows vulnerabilities to go unnoticed.

Radix-M addresses this critical market void by offering the first automated way to execute thorough security validation procedures for firmware and chip designs. When integrated with commercial emulation systems, such as the Cadence Palladium Z1 platform, Radix-M analyzes an entire software stack on the hardware, ensuring security simultaneously on both parts of the system.

System design and analysis tackles electromagnetic challenges

April 2, 2019 By Aimee Kalnoskas Leave a Comment

Cadence Design Systems, Inc. entered the fast-growing system analysis and design market with the announcement of the Cadence Clarity 3D Solver, which delivers high accuracy with up to 10X faster simulation performance and unbounded capacity compared to legacy field solver technology. Harnessing state-of-the-art distributed multiprocessing technology, the Clarity 3D Solver efficiently tackles electromagnetic (EM) challenges encountered when designing complex 3D structures on chips, packages, PCBs, connectors and cables — bringing true 3D analysis to any engineer with desktop, high-performance computing (HPC) or cloud computing resources.

The Clarity 3D Solver easily reads design data from all standard chip, IC package and PCB implementation platforms while also providing unique integration benefits for design teams using the Cadence Allegro and Virtuoso implementation platforms.Highly complex structures found in silicon interposers, rigid-flex PCBs and stacked-die IC packages must be modeled accurately in 3D for structure optimization and high-speed signaling compliance. High-speed signaling, such as in 112G serializer/deserializer (SerDes) interfaces, relies on high-fidelity interconnect design. Any slight change in impedance can negatively impact bit error rate, so optimization entails extensive research including dozens of complex extractions and simulations. To accommodate this workload, legacy field solvers must run on massive, expensive high-performance servers.

In addition, speed and capacity limitations of legacy field solver technology require users to carefully simplify and/or partition the structure into smaller segments to fit within local computing constraints. This pseudo-3D approach creates the risk that the resulting final model may contain inaccuracies due to artificial effects from the superficial model boundaries.

Clarity 3D Solver technology addresses the most complex EM challenges faced when designing systems for 5G communications, automotive/ADAS, HPC and IoT applications. Industry-leading Cadence distributed multiprocessing technology enables the Clarity 3D Solver to deliver virtually unlimited capacity and a 10X speed up required to efficiently and effectively address these larger and more complex structures. The Clarity 3D Solver creates highly accurate S-parameter models for use in signal integrity (SI), power integrity (PI) and electromagnetic compatibility (EMC) analysis, enabling simulation results that match lab measurement.

The Clarity 3D Solver is optimized to distribute a job across multiple low-cost computers while remaining equally efficient when running on a more powerful and expensive server with terabytes of memory. A unique distributed adaptive meshing approach and significantly smaller memory requirements than legacy 3D field solvers enable the Clarity 3D Solver to extensively utilize cost-effective cloud and on-premises distributed computing. These advantages make the cloud-ready Clarity 3D Solver an ideal choice to optimize a company’s cloud computing budget.

Using the Clarity 3D Solver in conjunction with the Cadence Sigrity^™ 3D Workbench, users can merge mechanical structures such as cables and connectors with their system design and model the electrical-mechanical interconnect as a single model. The Clarity 3D Solver is also tightly integrated with the Virtuoso, Cadence SiP Layout and Allegro implementation platforms, enabling 3D structures to be designed in the Allegro and Virtuoso environments, optimized in the analysis tool and implemented in the design tool without being redrawn.

Chip design tools optimized for Arm Neoverse N1 platform in cloud-to-edge apps

February 25, 2019 By Aimee Kalnoskas Leave a Comment

Cadence Design Systems, Inc. announced that its tools and IP have been optimized to support the new Arm Neoverse N1 platform to accelerate the transformation of a scalable cloud-to-edge infrastructure. To ease adoption, Cadence delivered a 7nm full-flow digital implementation and signoff Rapid Adoption Kit (RAK), collaborated with Arm to ensure the Cadence Verification Suite and its engines improve designer throughput, and integrated Cadence DDR4 PHY IP, CCIX IP and PCI Express® (PCIe) 4.0 PHY IP. Additionally, the Neoverse N1 System Design Platform (SDP), based on the Neoverse N1 platform and Cadence IP, was implemented and verified using Cadence tools to support Cache Coherent Interconnect (CCIX) for asymmetrical compute acceleration.

The RAK for Neoverse N1 includes the Cadence full-flow digital implementation and signoff tools that utilize Arm 7nm POP IP libraries. The comprehensive Cadence RTL-to-GDS flow enables customers to accelerate physical implementation and signoff to speed time to market. The RAK also includes comprehensive documentation and scripts outlining how customers can achieve optimal power, performance and area (PPA) goals with new devices. The tools in the flow include the Innovus Implementation System, Genus Synthesis Solution, Conformal Equivalence Checking, Conformal Low Power, Tempus Timing Signoff Solution and the Quantus Extraction Solution.

Cadence Verification Suite

Cadence delivered a full verification and emulation suite to support the Neoverse N1 platform including Xcelium Parallel Logic Simulation Platform, Palladium Z1 Enterprise Emulation Platform, JasperGold Formal Verification Platform, vManager Planning and Metrics, Perspec System Verifier and the Cadence Verification IP (VIP) portfolio with the Cadence Interconnect Workbench. The powerful combination of the Cadence Verification Suite and its engines improve verification throughput for engineers creating Neoverse N1-based designs.

Cadence IP

Cadence DDR4 PHY IP, CCIX IP and PCIe 4.0 PHY IP have been integrated and proven in silicon with the Neoverse N1 platform, driving key I/O interfaces to peak levels of performance. Arm selected the Cadence IP for the integration due to its strong feature set and maturity with silicon proof-points at 7nm.

Neoverse N1 SDP

Cadence also collaborated with Arm on the delivery of the Neoverse N1 SDP. The N1 SDP is based on the Neoverse N1 platform and Cadence DDR4 PHY IP, CCIX IP and PCIe 4.0 PHY IP that enables asymmetrical compute acceleration via CCIX for application areas like machine learning / artificial intelligence (AI), 5G and analytics. A full Cadence tool flow was used to implement and verify the SDP, and customers can begin software development immediately and shorten overall time to market.

Cache coherent interconnect for accelerators test chip will use 7-nm FinFET process technology

September 14, 2017 By Aimee Kalnoskas Leave a Comment

Xilinx, Arm, Cadence Design Systems, Inc., and TSMC announced a collaboration to build the first Cache Coherent Interconnect for Accelerators (CCIX) test chip in TSMC 7nm FinFET process technology for delivery in 2018. The test chip aims to provide a silicon proof point to demonstrate the capabilities of CCIX in enabling multi-core high-performance Arm® CPUs working via a coherent fabric to off-chip FPGA accelerators.

Accelerating applications in the data center is a growing requirement due to power and space constraints. Applications such as big data analytics, search, machine learning, wireless 4G/5G, in-memory database processing, video analytics, and network processing benefit from acceleration engines that move data seamlessly among the various system components. CCIX will allow components to access and process data irrespective of where it resides, without the need for complex programming environments.

CCIX will leverage existing server interconnect infrastructure and deliver higher bandwidth, lower latency and cache coherent access to shared memory. This will result in a significant improvement in the usability of accelerators and overall performance and efficiency of data center platforms, lowering the barrier to entry into existing server systems and improving the total cost of ownership (TCO) of acceleration systems.

The test chip, implemented on TSMC’s 7nm process, will be based on the latest Arm DynamIQ™ technology, CMN-600 coherent on-chip bus and foundation IP. To validate the complete subsystem, Cadence provided key I/O and memory subsystems, which include the CCIX IP solution (controller and PHY), PCI Express® 4.0/3.0 (PCIe®-4/3) IP solution (controller and PHY), the DDR4 PHY, peripheral IPs such as I2C, SPI and QSPI, as well as associated IP drivers. Cadence verification and implementation tools are being used to build the test chip. The test chip provides connectivity to Xilinx’s 16nm Virtex UltraScale+ FPGAs over CCIX chip-to-chip coherent interconnect protocol.

The test chip will tape-out in early Q1 2018 with silicon availability expected in 2nd half 2018.

Chip IP helps implement advanced infotainment, ADAS SoCs in 16-nm FinFET Compact technology

September 8, 2017 By Aimee Kalnoskas Leave a Comment

Cadence Design Systems, Inc. today announced it is delivering a comprehensive automotive IP portfolio for the TSMC 16nm FinFET Compact (16FFC) automotive process technology. This broad IP portfolio enables a host of applications ranging from in-vehicle infotainment, in-cabin electronics, vision subsystems, digital noise reduction and advanced driver assistance system (ADAS) subsystems and is registered in the TSMC9000A program.

The comprehensive IP portfolio incorporates the key IP needed to implement advanced infotainment and ADAS systems on chip (SoCs), and includes the Cadence flagship 4266-speed grade LPDDR4/4X DDR PHY and controllers and PCI Express® 4.0/3.0 (PCIe®4/3) PHY and controllers. This is complemented by subsystems supporting MIPI® D-PHYSM, USB3.1/USB2.0, DisplayPort, Octal SPI/QSPI, UFS and Gigabit Ethernet with TSN.

In order to support cost-effective automotive SoC designs, Cadence IP is area- and power-optimized for the AEC-Q100 Grade 2 temperature range, eliminating the need to carry Grade 1 power and area penalties into cost-sensitive automotive SoC designs. Cadence IP is designed to be ASIL-B ready and ASIL-C/D capable based on end users’ safety goals and safety requirements as outlined in the ISO 26262 standard.

“Renesas has been the world leader in providing automotive computing SoCs for a long time,” said Masahiro Suzuki, vice president of the Automotive Solutions Business Unit, Renesas Electronics Corporation. “We are seeing increased adoption of advanced MCUs in automobiles to accelerate autonomous driving, connected cars and electric vehicles. To address these trends in a timely manner, we have been working with Cadence on the development of physical IP using cutting-edge process nodes. Cadence has delivered advanced solutions for LPDDR4/4X PHY that support the highest LPDDR4 memory speed available in the market.”

“Cadence automotive subsystem solutions have been designed from the ground up to meet the stringent requirements of automotive OEMs and tier 1 suppliers,” said Babu Mandava, Cadence’s senior vice president and general manager, IP Group.” Additionally, Cadence IP is performance optimized for the advanced SoC designs for in-vehicle infotainment and ADAS applications. Through our continued collaboration with TSMC, we’re making it very simple for automotive designers to use the most advanced IP solutions to deliver innovative products to market quickly with confidence that they are compliant with the industry’s latest safety and reliability standards.”

“Cadence has quickly adapted its IP portfolio to support automotive applications for our 16FFC process, enabling accelerated design-ins with major automotive suppliers,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Our ongoing collaboration with Cadence has resulted in a robust, comprehensive set of IP that enables today’s complex automotive designs for ADAS applications and infotainment systems.”