Imperas Software Ltd., announced the latest enhancements to its range of RISC-V reference models and solutions to support processor verification, with the leading commercial SystemVerilog hardware design verification environments provided by Cadence, Mentor, Synopsys, and also the Metrics cloud-based tools. Working together with lead customers, industry groups and associations, and the Google Instruction Stream Generator […]
Instruction set simulator (ISS) for Mi-V RISC-V soft CPUs
Microsemi Corporation and Imperas Software Ltd. announced the Extendable Platform Kit for Microsemi Mi-V RISC-V soft central processing units (CPUs). The collaboration delivers the first commercially available instruction set simulator (ISS) for Microsemi’s Mi-V ecosystem, a program designed to increase adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs). “Building out the Mi-V RISC-V ecosystem with the Imperas […]
