The MIPS S8200 is a RISC-V neural processing unit designed to run transformer-based and agentic AI models directly on autonomous edge platforms. Developed with a software-first architecture, it supports early model optimization on virtual platforms and targets embedded transportation, robotics, and mission-critical systems requiring multimodal AI processing. The device is sampling now, with silicon reference […]
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MIPS releases multithreaded processor for edge computing
MIPS has announced that the MIPS I8500 processor is now sampling to lead customers. The processor was featured at GlobalFoundries’ Technology Summit in Munich, Germany. The I8500 is a data movement processor IP designed for real-time, event-driven computing platforms targeting hyperscale, storage, automotive, industrial, and communications infrastructure markets. The MIPS I8500 incorporates a scalable multithreaded […]
RISC-V core supports multi-sensor vehicle processing
MIPS announced the general availability(GA) launch of the MIPS P8700 Series RISC-V Processor. Designed to meet the low-latency, highly intensive data movement demands of the most advanced automotive applications such as ADAS and Autonomous Vehicles (AVs), the P8700 delivers industry-leading accelerated compute, power efficiency and scalability Typical solutions for ADAS and autonomous driving rely on […]
Scalable RISC-V multiprocessor IP promotes efficient SoC uses
As the shift toward RISC-V accelerates across industries, the open standard instruction set architecture (ISA) is ushering in a new wave of innovation and collaboration. In an effort to help fuel this trend, MIPS has announced the availability of the eVocore P8700, the industry’s highest-performance, most scalable RISC-V multiprocessor IP. The P8700 has already been […]
RISC-V multiprocessor IP cores boast high scalability
MIPS announces its entrance to the RISC-V market, previewing the first products in its eVocore product lineup. The new eVocore P8700 and I8500 multiprocessor IP cores are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard. The new eVocore multiprocessor IP cores are the first MIPS products based on the […]
