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Bluetooth direction finding brings a new dimension to indoor asset tracking

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By Mikko Savolainen, Senior Manager, Industrial and Commercial IoT Products, Silicon Labs

Since opening the Global Positioning System (GPS) for civilian use in the 1980s, GPS technology has become a mainstream and de facto solution for outdoor positioning and asset tracking, finding its way first from commercial airplanes to smartphones and smartwatches to match-box-sized GPS trackers. However, until recently, we haven’t seen an equivalent mainstream technology alternative to GPS for indoor asset tracking and positioning, although many attempts exist. The advent of Bluetooth direction-finding technology is now changing the landscape of indoor asset tracking and positioning applications and potentially driving mainstream adoption.

Many attempts to solve the RF-based indoor positioning and asset tracking challenges have been tried using technologies such as Ultra-Wide Band (UWB), Wi-Fi, or Bluetooth Received Signal Strength Indicator (RSSI)-based solutions. While these RF technologies can solve the challenge to a certain extent, they all have unique limitations, making them less than ideal options for indoor asset tracking.

UWB is probably the most widely used technology for indoor location applications. While it is known to deliver extremely good accuracy down to centimeters, the challenge with UWB is that it has not become a mainstream technology, which has kept IC and module prices high and limited the widespread use of the technology. In addition, the high power consumption of UWB radios limits the battery life of asset tags and increases the bill of materials (BOM) or maintenance cost for the tags.

Wi-Fi is another technology that has been used for RF-based indoor location services. While Wi-Fi offers the advantage of ubiquitous infrastructure, especially in retail and commercial spaces, to provide Internet access to laptops, smartphones, and other terminals, the RSSI-based positioning does not deliver high accuracy — typically limited to 5-10 meter accuracy. In addition, Wi-Fi primarily targets high-speed wireless data transfer, and it’s challenging to create low-cost, low-power Wi-Fi tags.

Since the introduction of Bluetooth Low Energy (LE) technology and beaconing standards such as Apple iBeacon and Google EddyStone, multiple attempts have been made to use Bluetooth LE for indoor location services. Bluetooth has the benefit of being a widespread, mainstream, and very low power technology. Low-cost asset tags or beacons can be built with Bluetooth, and they can easily provide a 5- to 10-year battery life even with coin cell batteries. Bluetooth LE is also widely adopted in smartphones and tablets, enabling these devices to detect assets. While there are successful large-scale deployments of Bluetooth beacon-based indoor location solutions, beaconing-based solutions also use RSSI-based positioning technology and have similar accuracy limitations as Wi-Fi RSSI-based solutions. There is also the need for Bluetooth-based infrastructure deployment.

Understanding Bluetooth direction finding technology

Bluetooth direction finding was introduced as part of the Bluetooth Core Specification 5.1 specification in January 2019. The purpose of direction finding technology is to enhance the positioning capabilities of Bluetooth technology by being able to detect the direction of the incoming Bluetooth signal instead of relying on simple transmit (TX) power and RSSI based mechanisms.

The core of the direction finding specification relies on two methods called the angle of arrival (AoA) (see Figure 1), and angle of departure (AoD). Both methods rely on at least one of the Bluetooth devices having an array of antennas and being able to receive or transmit the Bluetooth signal while shifting between the different antennas.

Bluetooth direction finding
Figure 1. Angle-of-Arrival operation

Figure 1. Angle-of-Arrival operation

With the AoA method, the next key step is to be able to measure and detect the Bluetooth signal phase differences (see Figure 2) between the different receiving antennas and then calculating the angle of the arriving signal from that information as well the known distance between the different antennas.

Figure 2: Deriving Angle-of-Arrival from signal phase differences at different antennas.

The AoA, as well as AoD technology, only provides a relative azimuth and/or elevation data between the transmitting and the receiving devices, and additional information is needed to compute the absolute X, Y and Z coordinates of the Bluetooth asset tag. Figure 3 shows a mechanism for achieving this capability. In this example, the receiver coordinates and orientation are known, and the AoA method is used to derive the azimuth and elevation data from the Bluetooth asset tag.

Figure 4. Example of an indoor asset tracking solution architecture.

 

There are other ways to compute the X, Y, and Z coordinates of the tracked device, such as using multiple receivers to detect the signal transmitted by the asset tag and then using triangulation or trilateration to compute the location of the assets.

State of Bluetooth direction finding technology

It’s one thing to have specifications and standards available but another issue to have working technology ready to be deployed for real-life applications. Let’s take a close look at state of the art for Bluetooth direction finding technology available today.

System architecture

A typical indoor positioning solution consists of at least three components: the tracked assets, the infrastructure needed to discover and track the assets, and a back-end system that is usually responsible for advanced position logic and management of the assets and/or the infrastructure.

Figure 4. Example of an indoor asset tracking solution architecture.

Assets

The easiest piece of the puzzle to solve is the assets. Bluetooth LE technology has reached a maturity point where Bluetooth radios are power efficient enough to run 5-10 years on coin cell batteries and enable dedicated asset tags to be built at a reasonably low cost. Wireless devices such as the Silicon Labs EFR32BG22 SoC also support the Bluetooth 5.1 standard and AoA and AoD technology.

Another interesting aspect with Bluetooth LE is that it is already integrated into many assets like medical equipment and power tools for smartphone connectivity and data transfer purposes and can enable turning on tracking on these devices at no extra hardware cost.

A more complex but mandatory piece of the puzzle is the tracking infrastructure. The asset tracking infrastructure requires the use of antenna arrays, AoA technology, and Bluetooth 5.1 compatible Bluetooth radios. As the Bluetooth 5.1 standard has only been available since January 2019, these devices are still not mainstream or widely available. However, the early adopters of this technology, such as Quuppa, already have AoA compatible infrastructure available, including Quuppa’s Q17 Bluetooth locator.

Bluetooth has also already found its way into commercial Wi-Fi access points and RSSI-based tracking solutions such as the Cisco Meraki MR53. These solutions are available at a relatively low incremental cost of RF switching and antenna arrays, and these devices could become Bluetooth AoA capable.

Infrastructure device vendors are implementing Bluetooth AoA technology into their products. For example, Silicon Labs has developed a Bluetooth 5.1 AoA reference design with a 4×4   antenna array matrix capable of receiving AoA transmissions from the tags and detecting azimuth and elevation down to a few degrees of accuracy.

Positioning and management engines

The last crucial component in any indoor location solution is the position and/or management engine responsible for computing and maintaining the location and status of the assets. Although there are multiple vendors with different position engine solutions using various technologies, only a few support Bluetooth AoA technology today due to the technology being relatively new. The most mature solution may be the QPE position engine provided by Quuppa. The QPE engine not only provides the X, Y, and Z coordinates of the tracked assets, but it can also collect and expose IoT data from the tags as well as provide a feedback channel back to the tags enabling asset tracking and two-way data transfer.

 

Conclusions

With direction finding technology, Bluetooth can enable accurate and affordable indoor asset tracking and positioning applications to become a mainstream solution over the next decade, similar to how opening up GPS infrastructure enabled outdoor tracking and positioning.

Bluetooth LE technology has reached a level of maturity at which the price points of Bluetooth radios make it commercially feasible to integrate Bluetooth into even disposable devices while providing a 5- to 10-year battery life on typical coin cell batteries.

The AoA infrastructure still needs to be developed and deployed further. Still, early adopters such as Quuppa already have solutions available, and Bluetooth has also found its way into commercial Wi-Fi infrastructure, such as Cisco’s Meraki devices. Leading silicon and software vendors are providing the mission-critical building blocks to help the infrastructure vendors implement and deploy the technology. The first AoA-capable position engines, including the Quuppa QPE, are already available in the market, and it is only a matter of time when such solutions will become widely available from multiple vendors.

 

About the author

Mikko Savolainen is a Senior Product Manager at Silicon Labs, where he is responsible for the marketing of Silicon Labs’ commercial lighting, indoor positioning, asset tracking and clinical medical solutions. Mikko joined Silicon Labs in February 2015 after the company’s acquisition of Bluegiga Technologies, a Finnish Bluetooth and Wi-Fi module and stack manufacturer. Before joining Silicon Labs, Mikko worked in various management positions at Bluegiga focused on marketing, product management and customer service operations. Mikko has a M.Sc. degree in engineering from the Aalto University in Espoo, Finland.

Simplifying product returns through device security

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by Oivind Loe, Chief Technology Officer, Sipsby.com, and Josh Norem, Staff Systems Design Engineer, Silicon Labs

Product returns for Internet of Things (IoT) devices can be challenging. On the one hand, connected the device should be locked down as much as possible when going out to the field. On the other hand, when a device fails in the field, you want the ability to open the device up to understand the root cause and remove the issue from future devices. Through new device security features, the best of both worlds can now be achieved.

As a device maker, you focus most of your attention on making the best product possible, making it attractive and valuable to customers, selecting the right materials, ensuring reliable manufacturing, and making sure the hardware and software are of high quality. You also take care of security and make sure the software can be updated in the field, so you can fix any issues that might come up. You might think that your job is now done, though, in fact, it has just started.

As more and more people use your devices, eventually issues are going to arise, and product success can often depend greatly on how you address these issues. Dealing with it poorly can result in angry customers, bad reviews, and eventually, a failed product. Dealing with it properly can make customers feel cared for, can sort out any issues with your product, and result in years of friction-free selling at large volumes.

Let’s take a closer look at the returns process and how failure analysis can be simplified through proper observability into the product without compromising product security and intellectual property (IP) protection.

Understanding product returns

A device can be returned to the device maker for several reasons:

  • The device was dead on arrival.
  • The device stopped working after some time.
  • The device exhibits wrong behavior.

When a product is returned, large customers or distributors will want to know the impact of the issue and how to resolve it.

  • What percentage of products are affected?
  • What is the failure rate (daily, weekly, or monthly)?
  • What is their exposure?
  • What is the root cause of the failure, and your plan to fix it? How can you be sure you have found it?
  • What do manufacturers need to do on their end to contain the problem for their operations or customers?
  • How can they be compensated for the issue?

A device maker must be able to answer all these questions and more. The “bathtub curve” shown in Figure 1 is a simple model for the failure rate of a product through its lifecycle. Through proper handling of product returns, early issues are dealt with and improved on quickly, while random and wear-out failures are efficiently identified and communicated properly. Note that all the failure components can be improved through engineering and cost tradeoffs, and acceptable failure-rate differs between product categories.

A potential challenge with product returns is that not all failing devices are returned. Often a customer will expect a certain failure rate, and frequently, the device-maker is not notified until the failure rate becomes significant. For mature products, this is not an issue as failures are often not due to product issues, but for new and ramping products, this can be problematic.

device security
Figure 1. The “bathtub curve” is widely used in reliability engineering and describes a typical view of device failures.

The internal process

Once a product return is received, the device maker needs to determine what priority to put on the investigation. Some products are returned as a courtesy with no real pressure to get to a resolution quickly, while others might have significant demands behind them. It is up to the company to determine what level of investigation is necessary based on the circumstance.

One way to approach a product return is with Eight Disciplines Problem Solving, also known as 8D, a method developed by the Ford Motor Company to resolve problems. The 8D process includes these key steps:

  • D0 – Problem summary including assessment of whether full 8D approach is necessary
  • D1 – Team formation
  • D2 – Problem definition
  • D3 – Containment plan – controlling impact while root cause and final solution are being determined
  • D4 – Root cause analysis – understanding the cause of the issue
  • D5 – Corrective action plan
  • D6 – Implement and validate corrective actions
  • D7 – Prevent recurrence
  • D8 – Sign off and commitment

Remedies to the problem come in two phases: Containment is the quick fix to minimize the impact of the issue and can be critical to resolving the problem in a timely manner. It can include but is not limited to halting firmware updates to devices, pulling affected inventory back from customers, implementing additional testing in production to catch the issue, and potentially stopping production altogether until the problem is solved. Being able to efficiently and accurately detect what products are affected can limit the negative impact of containment. In either case, communication with customers is key, as they are held responsible by their customers, and business relationships might be at stake.

The second phase of remedy is corrective action, applying the final fix to the problem once the root cause is understood. Finding the root cause of a problem can often be time- consuming and expensive, and there are cases where companies are unsuccessful in finding the root cause.

Note that an 8D may not be triggered based on product returns. It could also be triggered based on sudden increases in yield losses or other internally-discovered problems.

Failure analysis

Failure analysis or root cause analysis starts at the places that are a combination of easy to test and, based on experience, likely to reveal the root cause of many issues. This would often include visual inspection and running a product through production test to see if the device still passes or not. If not, that could indicate performance degradation in the field or intermittent product or test issues that were not caught during the first run-through.

Failure analysis goes on to other simple things, including looking for shorts, loose connections, and using probing tools to look for unexpected behavior. If a chip is suspected of having a problem, the chip could be replaced with a new chip or reprogrammed to see if the issue persists.

The most complex chip in a device is often the microcontroller or application processor. Unexpected behavior can be the result of several different causes, including but not limited to the following issues:

  1. Damage to the chip, either physical or electrical:
  • Soldering at wrong temperatures could lead to delamination issues.
  • Tensions in the PCB could crack the package and leads.
  • Submersion in liquids could cause formation of metal whiskers leading to shorts.
  • Improper handling could lead to ESD damage.
  1. Changed physical behavior due to wear-out:
  • Sustained operation of IOs outside current/voltage limits over time could alter their characteristics.
  • Significant transient voltage overshoot on pads could lead to damage.
  • Excessive writes to the same flash regions could wear out specific flash bit-cells.
  • Accelerated wear-out due to operation at high temperatures.
  1. Improper application behavior:
  • Incorrect or improperly programmed flash image (weakly programmed).
  • Incorrect application configuration or state in flash.
  • Application exposed to unexpected environmental inputs; sensor readings out of range.
  • Application bugs that were not discovered during testing.
  1. A problem with the chip itself:
  • Chips have a failure rate measured in parts-per-million. Some failures are expected. Excessive failure rates could be the result of a manufacturing issue.
  • Intermittent errors that only occur during certain conditions.
  • Consistent failures, i.e., a function that does not work as advertised.

The above causes can result in a wide range of failure modes or behaviors. Issues (1)-(3) are the most common, but issues of type (4) do occur, and identified problems are reported as chip errata so developers can work around them. The remaining sections in this paper primarily focus on ensuring enough visibility into the device to deal with issues of type (3) – improper application behavior. This also applies to specific issues of type (2), such as characterizing wear-out related issues and uncovering any issues related to the chip itself (3).

Chip locking

To analyze an application to get to the root cause of an issue, it is often very useful to be able to see what is going on inside the chip: to read the flash contents of the chip to see if the program, configuration information and state variables are correctly written, and observe the program while it is running. There is, however, a challenge with this approach.

There are many reasons why a device maker does not want to allow anyone to dig into the chip and observe the application. The firmware on the device could be company intellectual property; the device could contain secret information such network keys, end-customer personal information or credentials, or the application could monitor quantities the user would be charged for, such as a water meter monitoring how much water the user is consuming.

For these reasons, a chip is usually locked down when it leaves production to prevent anyone from being able to access the inside of the chip, often including internal company personnel who want to perform failure analysis.

The mechanism to lock down a chip comes down to a clear tradeoff between security, ease of failure analysis, and operational complexity. Table 1 shows seven methods of chip locking and tradeoffs, including a new method to be implemented in future Silicon Labs wireless IoT devices; using asymmetric keys to enable a good combination of security and ability to do failure analysis, which is also known as “Secure Debug Unlock.”

Secure debug unlock provides several benefits. Other locking schemes force the device-maker to make a trade-off between operational complexity, security, and the ability to perform efficient failure analysis. This method makes the process easy by not requiring device-independent secrets to be programmed, has a high level of security, and allows full access to the chip during failure analysis, which is key to understanding device problems quickly.

Operational difficulty describes how difficult the method is to implement by engineering and manufacturing. In-field risk describes how easy it would be for a hacker to gain access to the device in the field. Failure analysis describes how easy it would be for device-maker staff to gain access to the device for failure analysis.

table 1
Table 1. Methods of locking down a device and associated trade-offs.

Secure Debug unlock

To enable the secure debug unlock capability for a series of devices, the device maker creates an asymmetric key-pair. The public key is programmed into every device at manufacturing, and the private key is kept safe and secure in a way deemed sufficient by the device maker. A hardware security module (HSM) might be a good option.

To unlock a locked device, e.g., for failure analysis, the device maker queries the device for a debug unlock challenge, as well as the unique device ID. Using the challenge, a debug unlock token is created and signed with the private part of the debug unlock key-pair by the device maker. This debug unlock token can now be used by failure analysis engineers to unlock the part to get the ability to debug and continue with their root cause analysis. An overview of this process is shown in Figure 2.

Once the failure analysis is completed, a command can be run on the device to invalidate the unlock token, preventing it from ever being used again.

With the secure debug unlock approach, the device maker holds the key to the device. If the device maker believes there is something wrong with the chip itself and sends it to failure analysis by the chip vendor, the device maker would have to generate an access token for the chip vendor to have access to the device. This puts control entirely in the hands of the device maker while still providing full flexibility for performing proper failure analysis.

Secure debug unlock can be a key enabler for secure, quick, and efficient failure analysis for situations when the error cannot be found through inspection, and the recommendation is to enable it wherever possible.

Figure 2. Secure Debug Lock: Unlock Sequence

Conclusion

Dealing with field failures and other product issues are a natural part of building and selling embedded devices, and by dealing promptly and efficiently with issues that come up, a device maker can significantly improve the customer experience, product success, and business outcome. A solution must be chosen that provides full access to devices for failure analysis but without imposing a security risk or adding operational complexity. Locking a device using an asymmetric key, a technique that Silicon Labs calls “secure debug unlock” for wireless devices, maintains all the benefits of ensuring secure devices without adding complexity and risk.

PCI Express Gen 5 clocks and buffers lead in performance and power

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PCI Express Gen 5Silicon Labs has introduced a comprehensive portfolio of timing solutions that provide best-in-class jitter performance to meet the latest generation PCI Express (PCIe) 5.0 specification with significant design margin. The Si5332 any-frequency clock family generates PCIe Gen 5 reference clocks with jitter performance of 140 fs RMS, optimizing PCIe SerDes performance while meeting the Gen 5 specification with margin. The Si5332 clocks generate any combination of PCIe and general-purpose frequencies, enabling clock tree consolidation across a broad range of applications.

Silicon Labs also offers the Si522xx PCIe clock generators and Si532xx PCIe buffer families, which are capable of providing two, four, eight, or twelve PCIe Gen 1/2/3/4/5-compliant outputs, making them an ideal fit for clocking a wide variety of PCIe endpoints in data center applications.

Increasingly, data center hardware designs including network interface cards (NICs), PCIe bus expanders and high-performance computing (HPC) accelerators are using low-power 1.5 V or 1.8 V supplies to minimize overall power consumption. Powered from 1.5 – 1.8 V supply rails, the Si522xx and Si532xx devices are the industry’s lowest power PCIe clocks and buffers. The Si522xx and Si532xx output drivers leverage Silicon Labs’ proven push-pull high-speed current steering logic (HCSL) technology, which eliminates the need for external termination resistors required by conventional PCIe clocks using constant-current output driver technology.

Silicon Labs’ new clock products are fully compliant with PCIe Gen 5 Common Clock, Separate Reference No Spread (SRNS) and Separate Reference Independent Spread (SRIS) architectures. Despite PCIe Gen 5 having more stringent jitter requirements, Silicon Labs’ new products do not require discrete power supply filtering components, simplifying PCB layout while ensuring board-level noise does not degrade clock jitter performance. Board designers can seamlessly migrate existing PCIe Gen 1/2/3/4 designs with drop-in compatible Si5332, Si522xx and Si532xx clocks to easily upgrade existing designs to take advantage of faster PCIe serial interfaces.

The Silicon Labs PCI Express clock jitter tool has been updated to include the filters necessary to accurately measure PCIe Gen 5 reference clock jitter. This software greatly simplifies PCIe clock jitter measurement, ensuring the proper filters are applied as specified by the PCI-SIG Gen 1/2/3/4/5 common clock, SRNS and SRIS specifications while providing the results in an easy-to-read format. This user-friendly utility is available at no charge at silabs.com/pcie-learningcenter.

Samples and production quantities of the Si5332 any-frequency clock, Si522xx PCIe clocks and Si532xx PCIe buffers are available now. Samples ship in two weeks and production quantities are available in four weeks. The following pricing is for 10,000-unit quantities in USD:

  • Si5332 pricing ranges from $4.25 for the 6-output device to $4.90 for the 12-output device
  • Si522xx pricing ranges from $1.27 for the 2-output device to $2.76 for the 12-output device
  • Si532xx pricing ranges from $1.40 for the 4-output device to $2.10 for the 12-output device

The following development kits are available to provide quick, simple product evaluations:

  • Si5332 any-frequency clocks:  Si5332-6EX-EVB, priced at $149 (USD MSRP)
  • Si522xx PCIe clocks: Si52204-EVB, priced at $140 (USD MSRP)
  • Si532xx PCIe buffers: Si53208-EVB, priced at $175 (USD MSRP)

Clock IC,quartz-crystal reference combined in the same package

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Si5332
156.25MHz Output Clock Phase Jitter of 175fs RMS

Silicon Labs has expanded
its Si5332 any-frequency clock portfolio with new versions
combining the clock IC and a quartz crystal reference inside the same
package, simplifying board layout and design. The all-in-one Si5332 
solution guarantees reliable start-up and operation over the lifetime
of the product, unlike traditional solutions that source the clock IC
and crystal from different suppliers and risk interoperability issues.
Silicon Labs is also introducing multi-profile support available
across the entire Si5332 family, enabling developers to consolidate
multiple clock tree configurations into a single part number.

Traditional clock generators rely on an external, discrete quartz
crystal frequency reference. The crystal interface circuit must be
carefully designed for capacitive load matching to ensure accurate
clock synthesis. To minimize the risk of noise coupling, designers
typically do not route high-speed signals near crystals, which limits
printed circuit board (PCB) routing flexibility.

The Si5332 clock generator addresses these design limitations by
integrating a high-quality crystal reference inside the package. In
addition to simplifying design, this approach minimizes the overall
PCB footprint and maximizes PCB routing flexibility. The crystal is
shielded from external PCB noise, enabling the Si5332 integrated
crystal device to offer lower jitter (175 fs RMS 12 kHz to 20 MHz)
compared to versions of the Si5332 using an external source (190 fs
RMS).

“The Si5332 clock generator offers the industry’s highest level of
timing integration, enabling complete clock tree consolidation in
10/25/100G data center, communications, industrial and broadcast video
applications,” said James Wilson, General Manager of timing products
at Silicon Labs. “This comprehensive timing solution reduces supply
chain complexity since it’s sourced from a single supplier, Silicon
Labs.”

The Si5332 clock leverages Silicon Labs’ proven MultiSynth technology
to provide any-frequency, any-output clock syntheses with excellent
jitter performance. Supporting up to 12 clock outputs, selectable
signal formats per output clock (LVDS, LVPECL, HCSL, LVCMOS) and
independent 1.8-3.3V VDDO, the Si5332 interfaces to a broad range of
FPGAs, ASICs, Ethernet switches/PHYs, processors, SoCs, and high-speed
SerDes including PCIe. Collectively, these features enable the Si5332
to consolidate an entire clock tree in a single IC.

The new multi-profile feature takes timing integration to a new level,
enabling the consolidation of up to 16 unique clock tree
configurations in a single IC. A single Si5332 part number can now
replace crystal oscillator (XO) + buffer, clock generator, and clock
generator + buffer clock trees. Each unique configuration is
pin-selectable using hardware pins, eliminating the need for a serial
interface to reconfigure the device to support different frequencies.
Rather than sourcing different timing devices to support different
combinations of frequencies, the multi-profile feature streamlines
device qualification across different platforms and designs with a
single part number.

The Si5332 clock generators are supported by Silicon Labs’
ClockBuilder Pro (CBPro) software, which simplifies device
configuration and customization. With CBPro, customers can tailor a
clock solution to their specific requirements and receive samples in
as little as two weeks. CBPro generates a custom orderable part number
for each device with no minimum order quantity or non-recurring
engineering fees or restrictions.

Samples and production quantities of Silicon Labs’ Si5332 clock
generators are available now in a choice of 32/40/48-pin QFN packages
and 6/8/12-output options. Product pricing begins at $4.67 (USD) in
10,000-unit. Silicon Labs provides a wide range of evaluation boards
(EVBs) to accelerate device evaluation and development. Clock and
oscillator EVB pricing ranges from $149 to $199 (USD MSRP).

Software option simplifies in-field set-up of sub-GHz IoT devices

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sub-GHzSilicon Labs has released new software options for its Wireless Gecko portfolio, enabling simultaneous sub-GHz and 2.4 GHz Bluetooth Low Energy (LE) connectivity on a single chip. This Silicon Labs solution enables commercial and industrial IoT applications to combine long-range sub-GHz communications with Bluetooth connectivity, simplifying device setup, data gathering and maintenance. By avoiding the complexity of two-chip wireless architectures, developers can speed time-to-market and reduce bill-of-materials (BOM) cost and size by up to 40 percent. 

Silicon Labs’ new Wireless Gecko hardware and software solution enables users to set up, control and monitor sub-GHz IoT devices directly over Bluetooth with mobile apps. By adding Bluetooth LE connectivity to wireless networks in the sub-GHz band, developers can deliver new capabilities such as faster over-the-air (OTA) updates and deploy scalable, location-based service infrastructure with Bluetooth beacons.

Proprietary sub-GHz protocols are commonly used in low-data-rate systems, from simple point-to-point connections to large mesh networks and low-power wide area networks (LPWAN), where extended range, robust radio links and energy efficiency are top priorities. Sub-GHz connectivity is a good fit for long-range wireless sensor networks, smart metering, home and building automation, and commercial lighting. Silicon Labs’ Wireless Gecko solution makes it easy to add Bluetooth LE connectivity to these sub-GHz applications.

Silicon Labs’ new multiprotocol software is available now to customers using Silicon Labs’ EFR32MG and EFR32BG Wireless Gecko SoCs. Silicon Labs provides comprehensive software tools to simplify sub-GHz and Bluetooth development, including a connected lighting demonstration and a sample mobile application. Contact a local Silicon Labs sales representative or authorized distributor for EFR32 Wireless Gecko SoC pricing. To get started and learn more, visit www.silabs.com/dynamic-multiprotocol.

New study benchmarks Zigbee, Thread, and Bluetooth network protocols

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Zigbee, Thread, and Bluetooth Silicon Labs has released the industry’s first comprehensive network performance results based on large-scale, multicast testing of Zigbee, Thread , nd Bluetooth mesh software. Each mesh networking protocol presents unique characteristics and advantages, depending on the use case and end application. All testing was conducted at Silicon Labs’ Boston design center using the company’s Wireless Gecko SoC platform to eliminate the device itself as a variable in testing the mesh protocols.

 “Understanding the inner workings of mesh technologies helps developers assess how these network protocols perform in the key areas of power consumption, throughput, security and large network scalability,” said Daniel Cooley, Senior Vice President and General Manager of Silicon Labs’ IoT Products. “Zigbee, Thread and Bluetooth mesh are designed differently from the ground up, and we’re sharing our performance benchmark results to help developers select the right mesh connectivity option for their IoT designs.”

 The mesh network benchmark results can be used by system designers to define expected behavior for Zigbee, Thread and Bluetooth mesh in the 2.4 GHz frequency band. With the growing number of mesh networks available for IoT applications, it is important for developers to understand how these networks differ in terms of use cases and expected performance. The testing focused on device behavior and impact on battery life, network throughput and latency, and the impact of network size on scalability and reliability.

 Silicon Labs’ mesh network performance results are available as a series of application notes that define the methodology for performing the benchmark tests, enabling developers to replicate and run similar tests. These results provide guidance on mesh network design best practices and principles as well as expected field performance results. With 15 years of experience in mesh networking and more than 150 million deployed nodes, Silicon Labs is at the forefront of bringing advanced, multiprotocol wireless mesh technology to market.

 Silicon Labs’ mesh networking performance test results are available free of charge to developers at www.silabs.com/mesh-performance.

Wi-Fi devices cut power in half, bring security to battery-powered IoT applications

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Given the crowded field and reasonably mature market of Wi-Fi, it is noteworthy that Silicon Laboratories recently introduced a new Wi-Fi portfolio aimed at simplifying the design of power-sensitive, battery-operated Wi-Fi products including IP security cameras, point-of-sale (PoS) terminals and consumer healthcare devices.

Siddharth Sundar, Design Manager at Silicon Labs, explained, “We look at Wi-Fi from a different perspective. Most solutions come from suppliers with a cell phone or access point heritage — chips for heavy-duty media streaming, for instance. We come from the opposite side of mesh networking and wireless technology. As we worked with customers, we saw the need for IoT-friendly Wi-Fi solutions that accommodate the data, network, and battery constraints of these device. We took that technology and our low power and RF expertise and scaled it down for Wi-Fi devices in the IoT. The two new devices in this portfolio, the WF200 transceivers and WFM200, modules are built from the ground up with expertise from acquisition and legacy in communications.”

battery-powered IoT
The new Wi-Fi devices offer low transmit (TX: 138 mA) and receive (RX: 48 mA) power delivers 200 µA average Wi-Fi power consumption (DTIM = 3)

Optimized for exceptional energy efficiency, the WF200 transceivers and WFM200 modules support 2.4 GHz 802.11 b/g/n Wi-Fi while delivering the high performance and reliable connectivity necessary as the number of connected devices increases in home and commercial network

With the understanding that security is an evolving “thing” in the Internet of Things, Silicon Labs built a comprehensive security solution into the modules that disallows code that has not been signed and authenticated by Silicon Labs from running and keeps legacy firmware immune from hacks.

battery-powered IoT
Silicon Labs’ devices include secure booth and host interface, and hardware cryptography acceleration supporting AES, PKE, and TRNG.

“Naturally, there will be updates and patches that will that customers will apply. But our firmware and code are authorized with Secure Boot. And Secure Debug prevents unauthorized access to debug ports. So even if a vulnerability is found once a customer implements a patch, a hacker can’t roll back the firmware,” says Sundar.

The modules include standard host application, network, and wireless security protocols such as TLS, SSL, and WPA. Additionally, data transferred between host processor and WFx200 safeguarded with Secure Link to protect information like SSIDs and passwords.

According to IHS Markit, the market for Wi-Fi devices in low-power IoT end node applications is forecast to grow from 128 million units per year in 2016 to 584 million units per year by 2021. Developers can speed time to market and miniaturize battery-operated Wi-Fi products with the WFM200, the world’s smallest pre-certified system-in-package (SiP) module with an integrated antenna. Silicon Labs’ WF200 transceiver provides a cost-effective option for high-volume applications and gives developers the flexibility to meet unique system design requirements, such as using external antennas.

The energy-efficient WF200 transceiver and WFM200 module provide an array of benefits for Wi-Fi enabled IoT applications including: a small-footprint 4 mm x 4 mm QFN32 transceiver and 6.5 mm x 6.5 mm LGA52 SiP module, ideal for space-constrained applications; antenna diversity and wireless coexistence in crowded 2.4 GHz environment; pre-certification by the FCC, CE, IC, South Korea and Japan to minimize development time, effort and risk; and comprehensive development tools and wireless starter kit including embedded and Linux host drivers, enabling developers to get started quickly.

Silicon Labs is sampling WF200 transceivers and WFM200 SiP modules to selected customers, and production parts are planned for Q4 2018.

More information:  www.silabs.com/low-power-wi-fi

Check out this video with Sid Siddharth Sundar at Embedded World 2018 talking about the new transceiver and SiP modules:

I2C-programmable XOs provide superior jitter performance for 100/200/400G apps

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A new family of high-performance I2C-programmable crystal oscillators (XOs) are said to deliver best-in-class jitter performance and frequency flexibility. With typical jitter performance as low as 95 fsec, the Si544/Si549 Ultra Series programmable XOs maximize jitter margin for clocking high-speed 28 Gbps and 56 Gbps transceivers used in 100/200/400G communications and data center applications. The devices are capable of generating any frequency from 200 kHz to 1.5 GHz with no frequency gaps and four parts-per-trillion (ppt) tuning resolution, enabling a single device to work across a broad spectrum of applications.

Devised by Silicon Graphics, the Si544/Si549 XOs support up to four preset, pin-selectable silicon labs si54xstart-up frequencies. After power-up, the device operating frequency can easily be changed via an I2C interface. This configuration flexibility lets a single oscillator replace multiple single, dual and quad-frequency XOs and multiplexer (mux) devices. The device can be powered from a single 1.8, 2.5 or 3.3-V supply, eliminating the need for different XO part numbers for different supply voltages. The Si54x XO I2C interface supports update rates as high as 1 MHz (Fast-mode Plus), maximizing compatibility with a broad range of ASSPs, ASICs, SoCs and FPGAs.

The Si544/Si549 XOs are available in 3.2 x 5 and 5 x 7-mm standard, fixed-frequency XO packages. This compatibility enables hardware designers to prototype with an I2C-programmable XO and easily migrate to a single-frequency XO when the design transitions to production.

The Si54x XOs are purpose-built for 56 Gbps transceiver designs. These designs rely on pulse-amplitude modulation (PAM4) signaling for serial data transmission. PAM4 uses four-level signaling to boost the bit rate per channel while keeping the bandwidth constant. This tradeoff makes the design inherently more susceptible to noise. Using an ultra-low-jitter reference clock such as the Si544/Si549 devices maximizes signal-to-noise ratio (SNR) headroom, helps prevent bit-errors and helps maintain signal integrity.

The Si544/Si549 oscillators use advanced fourth-generation Silicon Labs DSPLL technology to provide an ultra-low-jitter clock source at any output frequency. On-chip power supply regulation provides power supply noise rejection, enabling consistent, reliable low-jitter operation in noisy environments often found in high-speed networking and data centers. The Si544/Si549 XOs also provide flexible, reliable drop-in replacements for low-jitter surface acoustic wave (SAW)-based oscillators while offering superior frequency tolerance and temperature stability. The Si544/Si549 oscillators support all popular output formats including LVDS, LVPECL, HCSL, CML, CMOS and dual CMOS.

In addition to the Si544/Si549 family, Silicon Labs is significantly expanding its XO/VCXO portfolio to include a broader array of package options. These complementary products include Si54x Ultra Series XOs in the industry-standard 5 x 7-mm package, Si59x general-purpose XO/VCXOs (3.2x 5 mm) and Si51x general-purpose XO/VCXOs (2.5 x 3.2 mm).

Samples and production quantities of the Si544/Si549 Ultra Series oscillators are available now. Silicon Labs offers two pricing levels for the Si54x family depending on the jitter requirements. Pricing in 10,000 unit quantities begins at $8.36 (USD) for Si549 XOs (95 fsec rms jitter) and at $6.69 (USD) for Si544 XOs (150 fsec rms jitter). The new Si5xxUC-EVB universal evaluation board, priced at $95 (USD MSRP), provides device evaluation.

Silicon Labs, 400 West Cesar Chavez, Austin, TX 78701,512-416-8500, 877-444-3032 (toll-free), www.silabs.com/ultra-series

Biometric sensors include advanced heart monitoring and ECG

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Capturing your heart rate from your wearable watch or patch was slick. But fitness enthusiasts are raising the bar and expecting manufacturers to step up to the bar with them.

As wearables continue to move into consumer health applications, end users are expecting additional metrics such as heart rate variability, recovery rate — basically as much detail as they can get. But, to-date, driving down power and improving sensitivity all while shrinking form factors have remained formidable challenges.

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Silicon Laboratories’ Si117x/8X biometric sensors enable HRM and ECG capabilities for wrist-based, patch-type and other wearables. The integrated module includes photodetector, four LED drivers, multiple LEDs, 12C and SPI interfaces, and 24-bit ADC

Silicon Labs recently introduced a family of optical biometric sensors that specifically address those power and sensitivity challenges, while adding the additional metrics consumers are demanding. The Si117x sensor modules provide advanced heart rate monitoring (HRM) along with electrocardiogram (ECG) capabilities for a wide range of wearable fitness and wellness products. The modules combine ultra-low power, high sensitivity and high integration, making them well-suited for smart watches and wrist-based, patch-type and other wearables requiring long battery life and enhanced HRM accuracy.

“These sensor modules showcase our increased broad sensor portfolio that is complementary to our IoT play for consumer health devices and wearables,” says Sid Sundar, Senior Manager for Sensors Products at Silicon Labs. “It speaks to our vision of how biometrics or physiological sensing is going to evolve over the next few years ago.”

The modules combine ECG measurements with optical HR measurements, allowing developers to unlock new potential biometrics for wearables. The ECG waveform is the gold standard for cardiac measurements, and the Si117x sensors bring this capability to wrist-based wearables in a cost-effective, power-efficient manner. By making measurements in the same device and at the same time, the Si117x sensors allow developers to combine biometrics with optical photoplethysmogram (PPG) measurements to derive valuable physiological parameters.

Typically abbreviated PPG, photoplethysmogram is an optically obtained plethysmogram, a volumetric measurement of an organ. A PPG is often obtained by using a pulse oximeter which looks at the intensity of reflected heart rate. To do that, you shine a constant light source and look at the reflected light which will detail a small variation as blood is flowing through. That variation is at the same frequency as a heart rate. About 99 percent of the reflected signal you get back is the constant signal but it is a small signal requring a great deal of sophi

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Si117x/8x Sensor Module Architecture

sticated digital processing — and a key problem when applied to a wearable device is to solve the motion artifacts. As device moves around your wrist, it causes changes that can create large variations making it more difficult to extract a signal. Accuracy is also compromised when you take into effect different temperature and skin tones.

 

Si117x sensors provide enhanced HRM accuracy for a better end user experience. The sensors offer fast sampling speeds, a high signal-to-noise ratio (SNR >100 dB), and the ability to cancel out ambient noise and erroneous data, resulting in high-quality signals that make it easier to track heart rates despite challenging physiologies, varying skin tones and the presence of tattoos. A more accurate view of the HR waveform enables biometrics beyond traditional HRM, including heart rate variability (HRV), stress analysis and pulse volume. By combining ECG with optical information, Silicon Labs’ sensor modules can extract measurements such as recovery rate that are normally difficult to pull out separately.

The Si117x module’s high level of integration address the additional challenge of optical design. Companies desiging wearables products may have plenty of EEs but few optical specialists. In addition to complexity of optical integration there is also complexity in term of software integration.

To simplify development and speed time to market, Silicon Labs offers a complete, end-to-end sensing solution featuring the Si117x sensor module, HRM algorithm, Wireless Gecko SoCs for Bluetooth connectivity, and an easy-to-use, wrist-based development kit with sample code and example projects.

Addressing the market need for power efficiency, the Si117x sensors consume less than 50 µA (sensor and LED combined) while performing continuous HRM. A built-in buffer and accelerometer synchronization capabilities save even more system-level power. The sensors’ industry-leading power efficiency enables developers to use smaller batteries in wearable designs without significantly impacting the device’s battery life during continuous monitoring.

The module’s high level of integration simplifies wearable design and makes it easier to synchronize multiple sensor measurements without adding significant system cost or board area. Each module supports up to four distinct LEDs (all of which can be driven simultaneously), and its four LED drivers are independently programmable (from 1.7 to 310 mA). Additional built-in features include a photodetector, 24-bit ADC with >100 dB dynamic range, I2C and SPI digital interfaces, programmable event interrupt engine, synchronization engine, host communications processor and inputs for two external photodiodes.

“As the market for health and fitness wearables continues to grow, developers want complete biometric sensing solutions that work flawlessly without the complexities of integration,” said Tom Pannell, Senior Marketing Director of IoT products at Silicon Labs. “Silicon Labs is the only supplier to provide a total HRM sensing solution in-house, from the sensor module and algorithm to the wireless SoC capable of transmitting measurements over Bluetooth LE. Our example HRM projects take care of interfacing between these components, and having a single point of contact greatly simplifies customer support and debugging.”

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Sensor options

The Si117x sensors support Silicon Labs’ proprietary, motion-compensated HRM algorithm optimized for wrist-based sensing and to run on EFM32 Gecko MCUs and EFR32 Wireless Gecko SoCs supporting Bluetooth Low Energy (LE). This unparalleled integration enables system-level power and performance optimization and reduces time to market for developers seeking to add HRM capabilities to their wearable designs.

Samples and volume quantities of the Si117x sensors are available in a 3.7 mm x 7 mm 28-pin LGA module. Silicon Labs also offers Si118x optical biometric sensors with an integrated photodiode in a clear 3 mm x 3 mm QFN package. To simplify development and performance evaluation, Silicon Labs provides a variety of wrist-based ECG and PPG development kits, a Bluetooth-enabled HRM evaluation watch, and an Android-based Triple Heart Application that captures data from multiple devices. Contact your local Silicon Labs sales representative for sensor and kit pricing. For additional information and to order sensor samples, visit www.silabs.com/hrm.

USB Type-C reference design simplifies design of lithium ion battery packs

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Silicon Labs has introduced a comprehensive reference design to simplify the development of USB Type-C rechargeable lithium-ion battery packs used to power smartphones, tablets, laptops, headphones and other portable devices. The reference design includes everything developers need to create dual-role port (DRP) applications with USB Type-C power delivery (PD), accelerating the development of new USB Type-C battery packs or migrating existing USB Type-A battery pack designs to USB Type-C. Silicon Labs’ USB Type-C Battery Pack Reference Design includes a development board, USB Type-C PD stack, example code, schematics and a hardware manual.

 The DRP battery pack reference design takes advantage of the PD stack included in Silicon Labs’ Simplicity Studio. The stack enables developers to make high-level function calls to negotiate and send USB Type-C messages to send or receive power. The flexible board design gives developers complete control over the battery application and includes a button used to change the power direction between sink and source mode.

 The Silicon Labs EFM8 Busy Bee MCU on the development board serves as a PD controller and provides exceptional design flexibility by negotiating a variety of power schemes. The reference design supplies 15 W (3 A @ 5 V) of power and charges at 1.8 A. The PD stack uses only a portion of the MCU’s capabilities, leaving many peripherals, memory and processing power available for developers to control regulators and power ICs, detect orientation, control switches, update other hosts on status and more. By using the EFM8 Busy Bee MCU as a PD controller, developers can incorporate other useful functions including an integrated temperature sensor and an analog-to-digital controller (ADC) to monitor the battery pack’s temperature and voltage to prevent overheating or overcharging.

 “We’re a mobile, connected society, and users need convenient rechargeable power sources for their smartphones, tablets and other portable devices,” said Tom Pannell, Senior Director of IoT Products at Silicon Labs. “Two-way, rechargeable battery packs are must-have products for people on the go, and our new turnkey USB Type-C reference design makes it incredibly easy for developers to create DRP charging solutions that are flexible, cost-effective and feature-rich.”