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Real-time voice-enhancement tech works with DSP design software

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Synopsys, Inc. and Alango Technologies today announced that Alango Technologies’ Voice Enhancement Package (VEP) software has been optimized for Synopsys’ DesignWare® ARC® Data Fusion IP Subsystem. The VEP is a suite of real-time software DSP technologies designed for improving speech recognition performance in voice-controlled multimedia devices. The ARC Data Fusion IP Subsystem is a highly integrated hardware and software IP product that processes data from sensor and audio sources with minimal energy consumption. The combination of Alango’s optimized audio signal pre-processing software with the ARC Data Fusion IP Subsystem enables designers to rapidly integrate a complete, pre-verified hardware and software solution for voice and speech processing into a range of multimedia devices requiring minimal energy consumption.

“The increasing prevalence of voice activation and recognition in human-machine interfaces is requiring sophisticated speech-to-noise ratio enhancement technologies to enable highly accurate speech comprehension in noisy environments,” said Dr. Alexander Goldin, CEO of Alango Technologies. “Optimizing our Voice Enhancement Package for the ARC Data Fusion IP Subsystem gives SoC designers an ideal low-power solution enabling superior voice activation, recognition and control capabilities in their products.”

Alango’s VEP is a suite of real-time software DSP technologies that includes a multi-microphone beamforming array and stereo echo canceller to enhance far-field speech pick-up and response to “barge-in” commands. The VEP is a front-end solution that performs audio signal pre-processing prior to the automatic speech recognition (ASR) and key word recognition (KWR) engines. The VEP receives the microphones’ signals, applies acoustic echo cancellation, and then forms acoustic beams relative to the usage environment or “field.” These acoustic beams, which have much-improved signal-to-noise ratio (SNR) compared to the raw microphone signals, are then sent to the ASR engine for recognition. VEP processing significantly improves the ASR’s ability to recognize verbal commands.

The ARC Data Fusion IP Subsystem is a pre-verified hardware and software solution optimized for highly efficient DSP performance and ultra-low energy consumption. The subsystem processes data from digital and analog sources, offloading the host processor to enable more efficient data processing. The configurable IP subsystem, with its choice of EM DSP processors, delivers a 2x performance boost for typical signal processing functions compared to other available processors and significantly reduces frequency and memory requirements to run audio codecs and speech/voice communication software. The ARC Data Fusion IP Subsystem also includes an audio processing library of common functions, including gain control, mixer and sample rate conversion. Tightly coupled PDM and I2S peripherals simplify the integration of voice and audio I/O such as MEMS microphones used for far-field voice user interfaces and hands-free voice commands. In addition, the hardware PDM interface implementation is significantly more energy efficient than the equivalent software implementation, with minimal gate count impact. The integrated solution is optimized for “always on” data fusion combining sensor, voice, gesture and audio processing functions.

“Advanced IoT devices are incorporating multiple microphones to enable more precise voice recognition by identifying the origin of a sound and cancelling interferences,” said John Koeter, vice president of marketing at Synopsys. “By combining our ARC Data Fusion IP Subsystem with Alango’s Voice Enhancement Package, designers can quickly integrate high-quality voice and speech capabilities into their SoCs while staying within their power and area budget.”

 

Logic libraries, embedded memory IP covers 40-nm ultra-low power, 40-nm low-power eFlash designs

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Synopsys, Inc. announced its collaboration with TSMC to develop foundry-sponsored DesignWare Foundation IP, including logic libraries and embedded memories, for TSMC’s 40-nanometer (nm) ultra-low power (ULP) eFlash and 40-nm low-power (LP) eFlash processes. Synopsys’ Foundation IP on TSMC’s 40-nm eFlash processes implements unique features that enable designers to reduce power consumption for IoT designs. The logic libraries include multiple channel gate lengths and ultra-low leakage standard cells to minimize leakage power, and offer power optimization kits and multi-bit flip-flops to achieve near-threshold operation down to 60 percent of nominal voltage. The embedded memories offer light sleep, deep sleep, and shut-down power management features for the lowest leakage, as well as assist circuitry to enable the lowest operating voltages. The DesignWare Logic Library and Embedded Memory IP on the TSMC 40-nm eFlash processes is available through Synopsys’ Foundry-Sponsored IP Program, which enables qualified customers to license the IP at no cost from Synopsys.

“TSMC continues to build on our long history of collaboration with Synopsys to deliver high-quality, proven DesignWare IP on a wide range of TSMC processes that help our mutual customers achieve their design objectives,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The availability of Synopsys’ Foundation IP for our 40-nm eFlash processes demonstrates how Synopsys continually invests in developing IP that enables designers to achieve the best power and area for their SoCs.”

“Synopsys and TSMC have worked closely together for many years to understand designers’ specific performance, power and area requirements for their target applications,” said John Koeter, vice president of marketing for IP at Synopsys. “By offering foundry-sponsored DesignWare Logic Library and Embedded Memory IP with differentiated low-power features for TSMC’s 40ULP eFlash and 40LP eFlash processes, we are enabling designers to improve energy efficiency and extend battery life of their IoT products.”

DesignWare Foundation IP for TSMC’s 40ULP eFlash and 40LP eFlash processes is scheduled to be available in 2017 at no cost to qualified licensees as part of Synopsys’ Foundry-Sponsored IP Program.

Low-energy PHY IP achieves Bluetooth 5 qualification

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Synopsys, Inc. announced that the silicon-proven DesignWare Bluetooth Low Energy Link Layer IP and PHY IP in industry-standard 40-nanometer (nm) and 55-nm processes have achieved Bluetooth 5 qualification and have been declared compliant by the Bluetooth Special Interest Group.

Achieving qualification ensures the robustness of the IP and that it functions as expected within a system-on-chip (SoC). The DesignWare Bluetooth IP solution has been validated with third-party software stack providers, including SEARAN, to provide designers with a complete hardware and software solution. The IP has been tested in third-party interoperability workshops to ensure that it operates reliably in real-world environments. The new, qualified DesignWare Bluetooth Low Energy PHY IP delivers up to 60 percent smaller area compared to the previous Bluetooth PHY solution, providing designers with a compact, low-power wireless IP solution for IoT applications such as medical, smart appliances, smart thermostats and wearables.

“SEARAN and Synopsys are addressing our mutual customers’ low energy wireless connectivity needs by providing a proven, complete Bluetooth 5 IP solution,” said Arkady Pittel, president and CEO at SEARAN. “The integrated solution, consisting of SEARAN’s compact dotstack and Synopsys’ DesignWare Bluetooth Low Energy Link Layer IP and PHY IP, allows designers to quickly bring differentiated Bluetooth-based products to the fast moving IoT market.”

Synopsys’ Bluetooth 5 Link Layer and PHY IP solutions support Bluetooth mesh and enable secure wireless connectivity with extended reach, and data rates up to 2Mbps with an integrated on-chip transceiver matching network. The PHY also supports the IEEE 802.15.4 standard for connectivity over wireless networks such as Zigbee or Thread. With more than 15 years of analog and radio frequency (RF) design experience and a portfolio of silicon-proven IP shipping in volume, Synopsys provides a robust wireless IP solution for integration into SoCs.

“Connected devices like wearables, smart locks, and smart thermostats require Bluetooth technology to communicate wirelessly at extremely low power,” said John Koeter, vice president of marketing for IP at Synopsys. “By providing a silicon-proven and qualified Bluetooth Low Energy Link Layer and PHY IP solution, Synopsys enables designers to integrate the required functionality into their SoCs to ensure compliance, interoperability, and robustness of their designs.”

The next-generation Bluetooth Low Energy PHY IP in 40-nm process is scheduled to be available in Q4 of 2017. Synopsys’ DesignWare Bluetooth Low Energy Link Layer IP and PHY IP in 40-nm and 55-nm are available now.

 

Processors optimize vision software for deep learning applications

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Synopsys, Inc. announced a collaboration with Morpho, Inc. to optimize Morpho’s computational photography software for Synopsys’ DesignWare EV6x Vision Processors. Morpho’s Scene Classifier image classification technology uses deep learning algorithms to analyze visual input and automatically apply tags for classification, searchability and organization. Morpho is optimizing their software to take advantage of the EV6x Vision Processors’ scalable hardware architecture, which includes up to four 512-bit vector DSPs and a fully programmable convolutional neural network (CNN) engine. The combined hardware-software solution enables designers to accelerate image classification and automated tagging tasks in their mobile and surveillance systems-on-chips (SoCs) while consuming significantly less power and memory resources than alternative implementations.

“We see growing demand for image processing software that takes advantage of deep learning networks to reduce computational resource requirements, particularly for battery-powered mobile devices,” said Masayuki Urushiyama, executive vice president at Morpho Inc. “Optimizing our deep learning and image processing software for the DesignWare EV6x Vision Processors enables designers to implement high-quality image recognition and classification solutions that increase the vision processing capabilities of their SoCs and consume much less energy than traditional GPU approaches.”

Morpho’s Scene Classifier uses deep learning to “recognize” essential identifying features for automated, real-time image tagging. Morpho’s portfolio of software algorithms includes high-precision scene recognition technology, motion detection, 360 VR stitching technology and other image processing technology. DesignWare EV6x Vision Processor IP is a family of fully programmable and configurable vision processors that integrate scalar, vector DSP and CNN processing units for highly accurate and fast vision processing. Supported by a comprehensive software programing environment including the ARC MetaWare EV Toolkit, the EV6x Vision Processors offer SoC designers a flexible, power-efficient embedded vision solution that addresses a wide range of automotive, industrial and consumer applications.

“The emergence of deep learning for image classification, detection and recognition enables a new level of image processing efficiency in SoC designs,” said John Koeter, vice president of marketing for IP at Synopsys. “By collaborating with Morpho to optimize their software for our EV6x Vision Processors, we are providing designers with a hardware-software solution that significantly improves the accuracy, performance and power consumption of image processing in power-sensitive applications.”

The DesignWare EV6x Vision Processors are available now. The Morpho Scene Classifier software optimized for EV6x Vision Processors is planned to be available in Q4 2017.

High-bandwidth memory 2 IP includes PHY, controller and verification facilities

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Synopsys, Inc. introduced its complete DesignWare High Bandwidth Memory 2 (HBM2) IP solution consisting of controller, PHY and verification IP, enabling designers to achieve up to 307 GB/s aggregate bandwidth, which is 12 times the bandwidth of a DDR4 interface operating at 3200 Mb/s data rate. In addition, the DesignWare HBM2 IP solution delivers approximately ten times better energy efficiency than DDR4. Advanced graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the increasing compute performance brought by advanced process technologies. With the DesignWare HBM2 IP solution, designers can achieve their memory throughput requirements with minimal power consumption and low latency. The new DesignWare HBM2 IP solution is built on Synopsys’ silicon-proven HBM and DDR4 IP, which has been validated in hundreds of designs and shipped in millions of systems-on-chips (SoCs), enabling designers to lower integration risk and accelerate adoption of the new standard.

“We selected Synopsys’ DesignWare HBM2 IP solution to take full advantage of the bandwidth and power efficiency of the 16GB of HBM2 memory in our Radeon™ Vega Frontier Edition graphics cards,” said Joe Macri, corporate VP and product CTO at AMD. “Synopsys’ deep expertise in memory interfaces enabled us to successfully integrate HBM2 IP into the ‘Vega’ GPU architecture and achieve aggressive power and memory bandwidth targets to serve machine learning and advanced graphics applications.”

The complete DesignWare HBM2 IP solution provides unique functionality that enables designers to achieve their memory bandwidth, latency and power objectives. The DesignWare HBM2 Controller supports pseudo-channel operation in either lock step or memory interleaved mode, allowing users to maximize bandwidth based on their unique traffic pattern. Both the HBM2 controller and PHY utilize a DFI 4.0-compatible interface to simplify integration with custom DFI-compliant controllers and PHYs.

The DesignWare HBM2 PHY IP offers four trained power management states and fast frequency switching that allows the SoC to manage power consumption by quickly changing between operating frequencies. The DesignWare HBM2 PHY enables a microbump array that matches the JEDEC HBM2 SDRAM standard for the shortest possible 2.5D package routes and highest signal integrity. To simplify HBM2 SDRAM testing, the DesignWare HBM2 PHY IP provides an IEEE 1500 port with an access loopback mode for testing and training the link between the SoC and HBM2 SDRAM.

Synopsys VC Verification IP for HBM is fully compliant to HBM JEDEC specification (including HBM2) and provides protocol, methodology, verification and productivity features including built-in protocol checks, coverage and verification plans, and Verdi protocol-aware debug and performance analysis, enabling users to achieve rapid verification of HBM-based designs.

“Increasing memory bandwidth without overtaxing power and area budgets is critical for graphics, HPC and networking applications,” said John Koeter, vice president of marketing for IP at Synopsys. “As the leading providing of memory IP, Synopsys has engaged closely with several lead customers to develop an HBM2 IP solution that enables designers to address increasing throughput requirements, with improved latency and power efficiency for their high-performance SoC designs.”

The DesignWare HBM2 PHY and VC Verification IP are available now for 14- and 7-nm process technologies, with additional process technologies in development.

Chip design IP emphasizes software integrity and security

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Synopsys, Inc. announced key updates to its Software Integrity Platform that are designed to help companies build security and quality into their software while reducing time-to-market. In the era of digital transformation, building secure and reliable software is challenged by the rapid, complex and diverse nature of development cycles. The latest updates to the Synopsys Software Integrity Platform address these challenges with expanded support for new programming languages, full coverage for the Motor Industry Software Reliability Association (MISRA) guidelines, improved automation and integration capabilities, and increased flexibility.

According to a recent Forrester Research report, “Applications are increasingly the face of interaction between companies and their customers; this includes customer-facing applications, differentiating mobile apps, Internet-of-things (IoT) device interfaces, and streamlined back-end processes. Meanwhile, application security technologies continue to evolve based on new developer methodologies, new attack vectors, new application types, and new business needs.”1

“The latest enhancements to the Synopsys Software Integrity Platform help organizations address the rapid pace of change when developing and securing their software,” said Andreas Kuehlmann, senior vice president and general manager for the Synopsys Software Integrity Group. “By expanding our coverage to include new programming languages and standards compliance, and ensuring our solutions integrate with a diverse ecosystem of development tools, we enable our platform to be adaptable to a wide range of customer needs. Synopsys is positioned to guide organizations along their software integrity journey as the industry landscape evolves.”

The new updates to the Synopsys Software Integrity Platform include a wide range of enhancements and features:

Expanded coverage: Organizations are expanding their software portfolios, resulting in the adoption of new programming languages, frameworks, and open source software components, while they are simultaneously navigating security, quality and compliance requirements. Empowering organizations to improve the security and quality of their broadening software portfolios, Synopsys continues to expand the coverage of its Software Integrity Platform.

  • Programming languages and analysis checkers –  The latest platform updates introduce Coverity® Static Analysis support for the Swift programming language, improved Protecode™ Software Composition Analysis support for open-source components written in Ruby programming language, and new eLearning courses for secure programming techniques in Android, iOS, and JavaScript. Synopsys has also expanded its static analysis offerings to detect a wider range of security and quality defects across all supported programming languages including Java and JavaScript.
  • Industry standards – Synopsys’ Static Analysis tool now provides full coverage for MISRA, a series of software development guidelines used by the automotive and other safety-critical industries to promote the safety and security of embedded systems. With this update, the Synopsys’ Software Integrity Platform now supports all statically verifiable rules in MISRA C 2004, MISRA C++ 2008, and MISRA C 2012.

Integration and automation: With the emergence of trends such as DevOps and continuous integration/continuous deployment (CI/CD), organizations are shifting toward more rapid and iterative development methodologies. To keep pace, software security testing efforts need to leverage automation and integrate with development tool chains and workflows. Synopsys continues to introduce news ways to automate the security and quality testing process, integrating it seamlessly with other development tools and workflows.

  • Synopsys updated its static analysis integration with CI/CD tools like Jenkins, as well as current versions of popular integrated development environments (IDEs), including Eclipse 4.7, Microsoft Visual Studio 2017, and IntelliJ IDEA. Integrating static analysis into development tools allows organizations to test early and often without disrupting their workflows or leaving their development environments.
  • Synopsys updated its software composition analysis solution to automate the confirmation of identified open-source software components, which accelerates adoption and time-to-value.
  • For its Managed Services for application security testing (AST), Synopsys added additional API enhancements to assist clients with automation of assessments. Organizations can manage their applications via the API, as well as export results and schedule assessments.

Flexibility: When it comes to making software secure, every organization has unique requirements and challenges that go beyond the confines of traditional out-of-the-box security solutions. Synopsys is committed to making its Software Integrity Platform flexible and customizable, giving companies the freedom to tailor the existing solutions to address new or special needs.

  • In this latest update, Synopsys introduced a Defensics® Fuzz Testing Software Development Kit (SDK) for building custom fuzz testing tools that detect critical security vulnerabilities in software applications and embedded devices. The SDK is built on the underlying technology of the industry leading Defensics Fuzz Testing tool, which was used to discover the infamous Heartbleed vulnerability. The Synopsys Fuzz Testing SDK is a powerful framework that provides companies the flexibility to test proprietary, niche or previously unsupported communication protocols and file formats.
  • Synopsys also added more flexibility to its eLearning solution, the self-paced security training component of its Software Integrity Platform. It has modularized the courses into bite-sized, consumable and mobile responsive modules, providing developers with focused training around a wide array of evolving technology stacks.
  • Synopsys added workflow enhancements to its Managed Services for application security testing to increase customer self-service and flexibility. Tests can now be removed from the queue and rescheduled quickly and easily. A new commenting feature was also introduced to the Managed Services workflow, providing a single location for customers and Synopsys consultants to communicate, ask questions, and provide updates. These updates enable Synopsys’ Managed Services offering to be more responsive to organizations’ changing needs, ultimately improving service utilization and value delivered.

Vision processors now handle high video resolution and frame rates for high-performance embedded apps

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Synopsys, Inc. announced that it has enhanced the convolutional neural network (CNN) engine in its DesignWare EV6x Vision Processors to address the increasing video resolution and frame rate requirements of high-performance embedded vision applications. The CNN engine delivers up to 4.5 TeraMACs per second when implemented in 16-nanometer (nm) FinFET process technologies under typical conditions, four times more performance than Synopsys’ previous CNN engine. It also supports both coefficient and feature map compression/decompression to reduce data bandwidth requirements and decrease power consumption. The vision CPU scales from one to four vector DSPs and operates in parallel to the CNN engine, delivering maximum throughput for a broad range of high-performance embedded vision applications such as advanced driver assistance systems (ADAS), video surveillance, augmented and virtual reality, and simultaneous localization and mapping (SLAM).

“The technological demands at the heart of embedded vision applications, in the neural network, require solutions that deliver the combination of high precision and performance with low power and area use,” said Toshi Torihara, vice president at Morpho US, Inc. “The unique combination of the vector DSPs and programmable CNN engine in the DesignWare EV6x Vision Processor enables developers to implement vision functionality in their embedded devices with much higher performance efficiency than CPU- and GPU-based alternatives.”

The DesignWare EV6x Processor family integrates scalar, vector DSP and CNN processing units for highly accurate and fast vision processing. The EV6x supports any convolutional neural network, including popular networks such as AlexNet, VGG16, GoogLeNet, Yolo, Faster R-CNN, SqueezeNet and ResNet. Designers can run CNN graphs originally trained for 32-bit floating point hardware on the EV6x’s 12-bit CNN engine, significantly reducing the power and area of their designs while maintaining the same levels of detection accuracy. The engine delivers power efficiency of up to 2,000 GMACs/sec/W when implemented in 16-nm FinFET process technologies (worst-case conditions). The EV6x’s CNN hardware also supports neural networks trained for 8-bit precision to take advantage of the lower memory bandwidth and power requirements of these graph types.

To simplify software application development, the EV6x processors are supported by a comprehensive suite of tools and software. The latest release of the DesignWare ARC® MetaWare EV Development Toolkit includes a CNN mapping tool that analyzes neural networks trained using popular frameworks like Caffe and Tensorflow, and automatically generates the executable for the programmable CNN engine. For maximum flexibility and future-proofing, the tool can also distribute computations between the vision CPU and CNN resources to support new and emerging neural network algorithms as well as customer-specific CNN layers. Combined with software development tools based on OpenVX™, OpenCV and OpenCL C embedded vision standards, the MetaWare EV Development Toolkit offers a full suite of tools needed to accelerate embedded software development.

“As high-performance neural networks become more prevalent in artificial intelligence applications, designers require both the hardware technology and software tools to deliver their vision-enabled SoCs on schedule,” said John Koeter, vice president of marketing for IP at Synopsys. “With the performance and feature enhancements to the silicon-proven EV6x Vision Processors, designers can more efficiently design and deploy machine learning-based applications with the performance and power efficiency necessary to differentiate in their markets.”

The DesignWare EV61, EV62 and EV64 processors with enhanced optional CNN engine are scheduled to be available in August 2017. The MetaWare EV Development Toolkit is available now. Support for the TensorFlow framework in the Toolkit’s CNN mapping tool is scheduled to be available in October 2017.

 

Chip design IP now works with 7-nm Leading-Performance (7LP) FinFET process

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Synopsys, Inc. today announced the enablement of the Synopsys Design Platform and DesignWare® Embedded Memory IP on GLOBALFOUNDRIES 7-nm Leading-Performance (7LP) FinFET process technology. Synopsys and GF collaboration on the new process addressed several new challenges specific to the 7LP process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF’s 14nm FinFET process. Designers of premium mobile processors, cloud servers and networking infrastructure can take advantage of these benefits by confidently deploying the silicon-proven Synopsys Design Platform and Embedded Memory IP.

“GF’s leading-performance 7-nm platform is exceeding initial performance targets and is now ready for customer designs,” said Alain Mutricy, senior vice president of product management at GF. “GF and Synopsys have collaborated to provide designers with tools and methodology that fully leverage the power and highest absolute performance of our 7LP technology, and will allow customers to create innovative products across a range of high-performance applications.”

GF and Synopsys worked together to ensure support of the comprehensive suite of Synopsys Design Platform digital implementation solutions for GF 7LP, including Design Compiler® Graphical synthesis, IC Compiler™ II place-and-route, IC Validator physical verification, PrimeTime® static timing analysis and StarRC™ extraction. To enable designers to achieve the full benefit of the GF 7LP process, the Synopsys tools employ advanced techniques including color track generation, pin color alignment checking and legalization, mixing of single-height and double-height physical boundary cells, power grid alignment to track and color-track aware routing.

The two companies are also collaborating on the development of Synopsys DesignWare Memory Compilers to deliver leading performance, power, area and yield for GF’s 7-nm process technology. This joint effort consists of optimizing the GF 7LP process design rules and line patterns to achieve the best results. Early versions of the memory compilers will be on the GF 7LP process qualification vehicle.

“Synopsys and GF have always worked closely to address our customers’ needs, including collaborations on FDSOI and 14-nm FinFET processes,” said Michael Jackson, corporate vice president of marketing and business development in the Design Group at Synopsys. “With today’s announcement, we are ready to enable designs on the 7LP process. We will continue to collaborate and ensure that our customers can get superior quality of results and faster time to results by using the Synopsys Design Platform and DesignWare Embedded Memory IP.”

Availability

Support for Synopsys Design Platform is available today for GF process technologies. The DesignWare Embedded Memory and Interface IP for the GF 7LP process are in development.

Verification IP, source-code test suite works with ARM AMBA 5 Coherent Hub Interface Issue B

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Synopsys, Inc. today announced the availability of its Verification IP (VIP) and source code test suite for ARM® AMBA® 5 Coherent Hub Interface (CHI) Issue B. Synopsys VC VIP for AMBA CHI has been widely adopted by SoC leaders for successful verification closure and tape out of coherent subsystems and interconnects. Synopsys VIP for the latest AMBA CHI Issue B specification enables customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance.

“Coherent systems are being adopted rapidly in a wide range of applications to scale performance with multiple processor clusters or I/O coherent accelerators and I/O,” said Andy Nightingale, vice president of marketing, systems IP, Systems and Software Group, ARM. “Collaborating on AMBA CHI Issue B VIP with our ecosystem partner, Synopsys, enables SoC teams to verify complex coherency-based designs with ease of use, and to increase productivity and performance for accelerated verification closure.”

AMBA CHI Issue B has added new features for atomic operations, cache stashing to improve data locality, new de-allocating and cache maintenance transactions and data check and poisoning to identify data corruption. AMBA CHI Issue B also provides direct data transfer to reduce latency.

Synopsys next-generation VIP provides performance metrics for latency and throughput analysis, a configurable interconnect model, a reference veri­fication platform and system-level checks for protocol, data integrity and cache coherency. The VIP is natively integrated with Synopsys’ Verdi® Protocol Analyzer debug solution. Built-in coverage and verification plans are also included to speed up verification coverage closure.

“Our Verification IP and interface IP solutions for ARM’s interconnect technology build on more than a decade-long collaboration for development of the latest AMBA protocol,” said Vikas Gautam, group director of VIP R&D and corporate applications in the Verification Group at Synopsys. “Our ongoing partnership with ARM continues to enable designers to create their next-generation server and networking devices with the latest AMBA CHI technology.”

 

New embARC open software platform enhancements support ARC HS processors, ARC SecureShield features

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Synopsys, Inc. announced the expansion of the embARC open source initiative to include a more comprehensive set of open source projects that help accelerate software development for DesignWare ARC processors. In addition, Synopsys has released a new version of the embARC Open Software Platform (OSP) that extends support to ARC HS processors as well as to the latest ARC SecureShield technology for the development of trusted execution environments implemented on ARC EM and ARC SEM processors. The comprehensive suite of free and open source software, including leading operating systems (OSes) such as FreeRTOS, the Zephyr Project and Linux, are available through the embARC.org website. The website gives software developers a central online location to download software, access upstream content, get documentation and join mailing lists for each open source project, simplifying the development of applications for ARC processor-based IoT and other embedded systems.

“Synopsys was one of the founding members of the Zephyr Project and has contributed to the Linux kernel for many years,” said Kate Stewart, senior director of strategic programs at The Linux Foundation. “Now, Synopsys is taking that support a step further by making the Zephyr Project and other open source projects easier to access for developers looking to get started quickly creating software for ARC-based IoT devices such as connected sensors, LED wearables, modems and wireless gateways.”

embARC.org is a dedicated website that provides developers centralized access to free and open source software, drivers, operating systems and middleware supporting ARC processors. Additionally, it provides access to GitHub repositories containing software maintained by Synopsys to enable developers to use and contribute to those open source projects. embARC.org supports leading operating systems, including FreeRTOS, Linux and the Zephyr Project, giving developers a choice of industry-standard software environments and the ability to select the OS that best fits their needs for their ARC-based systems.

Additional RTOSes, including Contiki, LiteOS and RIoT, which have been specifically developed for IoT edge devices have been ported to ARC EM processors. They are available from embARC.org and run on the ARC EM Starter Kit.

The embARC OSP includes the major protocols used in IoT devices today, networking stacks such as lwip, and commonly used security protocols including MatrixSSL, WolfSSL and TinyDTLS. The latest version of embARC OSP includes the OpenThread protocol, an open source implementation of the Thread networking protocol released by Nest Labs, Inc. The Thread specification is defined by the Thread Group and describes an IPv6-based protocol designed to be reliable, secure and low-power for wireless device-to-device communications for digital home applications. The embARC OSP also adds support for the ARC HS processors and includes an update to the SecureShield libraries that allow creation of a trusted execution environment on ARC EM and ARC SEM processors.

The ARC EM Starter Kit and the AXS103 Software Development Platform are available now.