ultrasoc

New IP adds hardware-based layer of security into CAN Bus

February 25, 2020 By Aimee Kalnoskas Leave a Comment

UltraSoC today announced a significant boost to its automotive cybersecurity offering with the launch of the CAN Sentinel; new IP that adds a much-needed hardware-based layer of security into CAN Bus, the global industry-standard interconnect for automotive manufacturers and OEMs. The UltraSoC CAN Sentinel resides on the bus, monitoring transactions with a vehicle’s electronic control units (ECUs), identifying suspicious activity, preventing malicious messages and silencing attacks.

CAN Sentinel is configurable with user-defined security rules, providing protection against common exploits such as frame spoofing, and allowing the system to be upgraded as the threat landscape evolves. Developed as part of the Secure-CAV Consortium of which UltraSoC is a leading member, it integrates with the wider UltraSoC secure embedded analytics and monitoring architecture, enabling the implementation of powerful system-wide cybersecurity protection.

Since its invention 30 years ago, the CAN (controller area network) bus has become ubiquitous in the automotive industry. More recently it has also become recognized as possibly the most serious security vulnerability in cars. A number of high-profile attacks – for example, the Miller-Valasek Jeep hack – have exploited its inherent lack of security features. Cybersecurity is an increasing concern for the automotive industry, being a prime cause of product recalls: estimated to have cost the industry $26 billion in 2016, when GM alone recalled 23 million vehicles in one year.

The launch of the CAN Sentinel follows hot on the heels of the UltraSoC Bus Sentinel, the first product in the company’s line-up of cybersecurity hardware. This was launched in late 2019 to simplify the embedding of a secure monitoring architecture into the heart of mission-critical and safety-critical devices, particularly in applications such as connected and autonomous vehicles (CAVs). These new cybersecurity hardware IP products combine with UltraSoC’s secure embedded analytics architecture to provide a complete holistic embedded security solution.

PCIe and Gigabit Ethernet connectivity added to embedded analytics architecture

November 21, 2019 By Aimee Kalnoskas Leave a Comment

UltraSoC announced new high-speed communications capabilities within its embedded analytics architecture, supporting debug and performance optimization in datacenters, high-performance computing, AI and storage applications. The addition of PCIe and gigabit Ethernet connectivity gives developers and users access to fine-grained information about the real-world behavior of such products, both in-lab during product development, and in-life after products are deployed in the field.

Ethernet and PCIe are the most common standard communications formats in use in today’s compute-intensive and performance-critical systems. They are therefore a natural choice for transporting the high volumes of data that engineers need to capture and analyze when profiling and optimizing the performance of such systems.

UltraSoC’s on-chip monitoring and analysis infrastructure provides an in-depth, cycle-by-cycle view of the internal operation of any system-on-chip (SoC) – and of the system surrounding it. This provides unmatched insights into the system’s behavior, but can generate large volumes of data. The addition of fast interfaces helps deal with these big data issues in two distinct use cases. First, as part of the development and debug process for new SoC designs, engineers need to capture, record and analyze the internal behavior of their chips – which often contain multiple heterogeneous processor cores.

Second, system designers and users of high-performance systems such as storage and HPC platforms need to optimize overall system performance under real-world conditions both in the lab and in the field. To achieve this they need to understand the real-world behavior and interactions between the many chips within the overall system, and the software running on them.

Both of these use cases can generate very large data sets, which need to be transported quickly and efficiently.

High-speed connectivity augments the existing embedded intelligence and data compression capabilities within the UltraSoC architecture, which includes hardware-level filters and counters, allowing engineers to home in efficiently on the aspects of the system’s behavior that really matter. Despite this high level of on-chip intelligence, hardware-based behavioral monitoring generates significant volumes of data that need to be transported on- and off-chip. UltraSoC is utilizing PCIe (2 Gbps per lane) and gigabit Ethernet (1 Gbps), making it possible for developers and end-users alike to access and analyze data across complex multicore, hyper scale applications – both in the lab and during operation in the field.

The UltraSoC PCIe and gigabit Ethernet solutions, incorporating IP modules and reference software, are available from Q4 2019 to lead customers.

Hardware-based cybersecurity products detect, block and record attacks, prevent propagation

October 8, 2019 By Aimee Kalnoskas Leave a Comment

UltraSoC announced next-generation hardware-based cybersecurity products that can be used to detect, block and record cyber-attacks in a broad range of applications – from vehicles and factory robots to consumer devices.

These new offerings embed advanced real-time cybersecurity features in the systems-on-chip (SoCs) that power and control every modern product. The first product in the range, the UltraSoC Bus Sentinel, allows SoC designers to control access to sensitive areas of their devices, instantaneously detect and block suspicious transactions, and build a long-term profile of system operation to secure against current and future cyber threats.

UltraSoC’s security solutions allow designers to incorporate an independent internal monitoring system into their chips. This continuously checks that the device is operating as expected, detecting anomalous behavior that might indicate a security breach. Because it is embedded in the hardware, it can respond in real time (in microseconds rather than the milliseconds required by traditional threat mitigation measures), is very hard to subvert or circumvent, and can even block “zero-day” type attacks that the chip’s designers have not anticipated. In addition to detecting and blocking cyber threats, it can be used to trigger actions that prevent propagation, and to provide a forensic “black box” record of events.

The new Bus Sentinel module monitors and controls the internal bus of an SoC, observing how the chip’s interconnected sub-blocks are interacting. It can be configured at run time to detect specific transaction types; for example, if a process tries to access the control registers of the memory controller at any time other than a system re-boot; or if a process with insufficient privileges attempts to access a protected area of memory. The detection process itself is performed via a range of configurable filters which can be cascaded to implement complex conditions and detect even very subtle nuances of system behavior.

In addition to its detection functions, the Bus Sentinel can be configured to respond to threats in a variety of ways, also in real time: it can allow the transaction to proceed unmodified; it may block the transaction from proceeding beyond the monitor using a transaction gating technique; it can modify the transaction in some way – for example by marking it with a flag; and it can generate a response on the bus. It can also issue a trigger event across the dedicated UltraSoC communications fabric, allowing an immediate response to be generated by other system blocks, or by external threat mitigation systems.

The Bus Sentinel’s system of filters, counters and timers allows it to be configured to detect common known security threats. These powerful capabilities give the system designer a wide variety of approaches to any given threat vector. Suspicious transactions can be detected and flagged, and subsequent transactions monitored without the attacker’s knowledge, to profile the threat. Transactions can be blocked, with the option to respond to the initiator and gather further information. Or the Bus Sentinel can trigger a response anywhere else within the on-chip system, communicating via the dedicated UltraSoC communications fabric.

The Bus Sentinel is equipped with storage units that can record data for use by the filters in future transaction identification. It can also be used in concert with the overall UltraSoC infrastructure to gather rich statistical data. This can be used by an on-chip analytics engine, or passed to an external cloud-based analytics system, to profile the system and produce a “signature” of normal behavior based on many deployed instances of the device. This, in turn, allows the threat mitigation system to adapt to the rapidly evolving threat landscape.

The UltraSoC Bus Sentinel will be generally available in Q1 2020. Its modular design allows it to support any bus protocol, with immediate support for commonly-used on-chip buses including Arm APB, AHB, AXI-4, and ACE.

Analytics architecture addresses complex multicore systems

February 15, 2019 By Aimee Kalnoskas Leave a Comment

UltraSoC announced a significant extension of its embedded analytics architecture, allowing designers and innovators to incorporate powerful data-driven features into their products. Developers in the automotive, storage and high-performance computing industries can now integrate even more sophisticated hardware-based security, safety and performance tuning capabilities within their products, as well as reaping substantial time-to-market and cost benefits of using UltraSoC in the system on chip (SoC) development cycle.

The new features allow SoC designers to build on-chip monitoring and analytics systems with up to 65,000 elements, allowing seamless support for systems with many thousands of processors. Future iterations will allow even higher numbers of processors for Exascale systems. In addition to this dramatically improved scaling capability, new System Memory Buffer (SMB) IP allows the embedded analytics infrastructure to handle the high volumes of data generated by multicore systems, and to cope with “bursty” real-world traffic.

The new UltraSoC architecture is capable of monitoring effectively unlimited numbers of the internal building blocks that make up the most complex SoC products – and to analyze the impact on system-level behavior of the interactions between them. Such heterogeneous multicore chips are becoming increasingly common, particularly in enabling the artificial intelligence and machine learning technologies required in leading-edge applications such as driverless cars.

UltraSoC’s system-level monitoring and analytics capabilities extend beyond the chip’s core processing components to all parts of the system – which may include thousands of IP blocks and subsystems, buses, interconnects and software. The new features within the UltraSoC architecture allow chip designers to deploy tens of thousands of monitoring and analytics modules within a single infrastructure. By providing an integrated, coherent analysis of the behavior of the system, UltraSoC significantly reduces the development burden for next-generation machine learning and artificial intelligence applications, as well as allowing the implementation of innovative product features such as hardware-based security and functional safety.

Extension of the UltraSoC architecture to encompass effectively unlimited monitoring capabilities helps developers to address the problems of systemic complexity which are among the most pressing issues faced by the electronics industry today. In addition to the sheer size of modern SoCs, machine learning and artificial intelligence algorithms are often inherently non-deterministic: because they devise their own ways of solving problems by ‘learning’, it is impossible for the system’s original designer to predict how they will behave in the final application. In-life monitoring of the chip’s behavior is therefore the only way of getting a true picture of what is going on inside the chip, and the wider system.

The complex interactions between multiple hardware blocks, firmware and software within SoCs have already made real-time in-life monitoring an indispensable tool for SoC designers. Changes in design approaches are also making system-wide monitoring more necessary than ever. Agile software development and ad hoc programming practices inherently require high-granularity visibility of the real system. Similarly, system hardware and software may not be ‘architected’ in the traditional sense: again, engineers need clear visibility of the run-time behavior of their systems.

The new UltraSoC analytics and monitoring architecture will be readily configurable within UltraSoC’s UltraDevelop 2, the company’s new IDE (Integrated Development Environment), announced recently and to be rolled out to customers from Q1, 2019.

Lockstep monitor supports any processor architecture or subsystem

November 29, 2018 By Aimee Kalnoskas Leave a Comment

UltraSoC has launched the UltraSoC Lockstep Monitor, a hardware-based, scalable solution that helps functional safety significantly by checking that the cores at the heart of a critical system are operating reliably, safely and securely. UltraSoC’s flexible IP supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and voting with any number of cores or subsystems.

The UltraSoC Lockstep Monitor can support any processor architecture or other subsystems, including custom logic or accelerators. Lockstep operation is needed for safety standards such as ISO26262 for automotive, IEC 61508, EN50126/8/9 and CE 402/2013.

mLockstep Monitor consists of a set of configurable semiconductor IP (SIP) blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution and even register states, between two or more redundant systems. It can be used with any processor architecture, including those – such as the emerging RISC-V architecture – which lack native support for lockstep configurations. In addition to traditional processor cores, it can also check other subsystems or accelerators. Because it is implemented in hardware, it responds at wire speed and imposes no execution overhead on the host system.

Included are flexible, run-time configurable embedded intelligence, allowing the SoC designer to tailor the monitoring and response system precisely to the application. Monitoring can be implemented at a variety of levels of granularity: at the subsystem level (comparing the outputs of the two processors); at the transaction level (for example comparing bus traffic); at the instruction level, using UltraSoC’s advanced instruction trace capability; and at the most fundamental hardware-level, checking processor internal states or register contents.

By embedding intelligence in the system, UltraSoC also allows more sophisticated comparisons between the operation of the lockstep processors than can be achieved with traditional solutions. For example, if the lockstep processors share a memory space, they cannot operate in perfect, cycle-by-cycle synchronization. UltraSoC’s on-chip analytics can be used to correlate activity within the redundant processors, and to tailor the response of the system depending on the nature of any detected anomalies.

RISC-V is gaining increasing traction in safety-critical applications, particularly in the automotive industry. However, the RISC-V ecosystem as a whole currently lacks support for the functional safety and security principles – such as lockstep operation – mandated by global standards such as ISO26262 for functional safety, J3061 for cybersecurity, IEC 61508, EN50126/8/9 and CE 402/2013. UltraSoC’s Lockstep Monitor allows any RISC-V system, whether using open source or commercial cores, to incorporate sophisticated safety capabilities. The company will be presenting on automotive safety and security – jointly with ResilTech, the specialists in resilient computing for critical systems –at the upcoming RISC-V Summit (Santa Clara, 3 – 6 Dec 2018).

Lockstep systems employ two or more processor subsystems running the same code in a redundant backup configuration. The cores may be clock-cycle synchronized, or offset by a small number of cycles, an arrangement that protects against transient errors in the surrounding system. The outputs, code execution or bus traffic from the subsystems are compared and if the results differ, an error can be signaled. Lockstep systems with two processors are typically configured in a ‘master/checker’ arrangement; those with more than two processors may use ‘voting’ or other redundancy schemes. More sophisticated “split/lock” processor arrangements may allow the lockstep function to be dynamically engaged and disengaged, allowing the cores to run in redundant mode or to run different code for higher performance.

IDE provides actionable insights for SoC development and debug

October 16, 2018 By Aimee Kalnoskas Leave a Comment

UltraSoC today announced UltraDevelop 2, a complete integrated development environment (IDE) that combines comprehensive debug, run control, and performance tuning with advanced visualization and data science capabilities for system-on-chip (SoC) development teams. Incorporating technology from UltraSoC partners Imperas and Percepio, UltraDevelop 2 provides actionable insights to dramatically cut development costs, shorten time-to-revenue and improve product quality.

The new UltraDevelop suite delivers a holistic, system-level approach to SoC development and debugs, allowing engineers to view and analyze the interlinked behavior of hardware, firmware and software at any level of abstraction – and to interactively switch between views and tools depending on the task at hand. UltraSoC’s newly developed data science extensions offer advanced capabilities such as anomaly detection, heat mapping and root cause analysis. Visualization capabilities based on Percepio’s Tracealyzer provide engineers with an integrated view of the operation of hardware and high-level software execution. The inclusion of Imperas’ MPD debugger enables support for today’s multi-core, multi-threaded platforms, including devices that combine cores based on different CPU architectures into complex heterogeneous systems.

Based on the industry-standard Eclipse platform, UltraDevelop 2 provides an integrated view that encompasses single step and breakpoint code execution status for multiple processors; instruction trace; and real-time, protocol-aware monitoring of hardware structures within the SoC. Engineers can simultaneously view the behavior of hardware structures such as memory controllers and interconnects / NoCs, and the execution of software, all across a number of different cores, even with different architectures. Designers working on simpler single-core debug tasks can access the same integrated debug capabilities while utilizing the open-source GDB debugger.

UltraDevelop 2 is architected to give SoC designers an optimal blend of functionality and flexibility in their choice of development platform. The tools include a library of debug adapters to enable real-time run control of more than 20 processor core architectures from multiple vendors, including Arm, MIPS and RISC-V (as implemented by Andes, Esperanto and SiFive), amongst others. Within the unified Eclipse environment, teams can choose to deploy third-party tools from existing UltraSoC partners such as Lauterbach, with support for the underlying UltraSoC hardware capabilities; or they can opt for a pre-integrated configuration supplied by UltraSoC.

UltraSoC’s vendor-independent, system-level approach to hardware/software debug is significantly enhanced by the addition of new analytics and data science capabilities. UltraDevelop 2 is supplied with a suite of modules that facilitate detailed big data analysis of on-chip behavior, including anomaly detection, heat mapping and root cause analysis. These include example applications and configurations for functional safety (for example the stringent verification and validation mandated by ISO26262 and other standards); cybersecurity (detecting vulnerabilities or unwanted interactions); and performance optimization (for example identifying inefficiencies in multi-threading software stacks, and hard-to-find states that lead to “long-tail” bugs in high-performance computing environments).

UltraDevelop 2 users can extend these capabilities, customize the framework and configure test systems via a range of scripted (Python) modules that give direct access to the data provided by UltraSoC on-chip monitors. These also provide configuration options and higher-level functionality such as terminal services.

Debug probes support RISC-V, Arm and other CPU platforms

August 2, 2018 By Aimee Kalnoskas Leave a Comment

UltraSoC announced that it has partnered with SEGGER to offer support for J-Link debug probes within UltraSoC’s integrated system on chip (SoC) monitoring and analytics environment. SEGGER’s J-Link probes are amongst the industry’s most widely-used and support the debug of popular processor platforms including RISC-V, and both current and legacy Arm cores. The partnership gives SoC developers easy access to J-Link via a single interface when debugging using UltraSoC’s flexible on-chip monitoring and analytics infrastructure.

UltraSoC is providing an open and accessible vendor-agnostic environment that suits the preferences of individual engineers in terms of processor architecture, development tools and hardware. In supporting the widest range of platforms and tools within its framework, UltraSoC opens the advantages of its embedded analytics platform to more designers, who benefit from faster development time, accelerated debug, and reduced risks and costs.

The integration of full support for SEGGER’s J-Link probes means that probe configuration and debug monitoring can take place under a single environment. In using UltraSoC’s embedded analytics, designers will get insights into the CPU’s operation, both during the design process and later in-field, as part of the wider system design.

UltraSoC CEO Rupert Baines commented, “Chip designers, like all engineers, want to be able to select the best tools for the job. At UltraSoC we are committed to partnering with best-in-class hardware and software vendors to ensure our mutual customers can maximize their potential for productivity and innovation. As one of the leading names in our industry, SEGGER fits perfectly within that strategy. As we support more and more customers on the open-source RISC-V platform, the need for flexibility and openness increases significantly. The industry is changing, and collaboration across the ecosystem is now more essential than ever.”

Harald Schober, Director Sales/Marketing at SEGGER, adds: “We are delighted to be working with UltraSoC – we share the commitment to provide the best tools to support designers of the key proprietary and open-source CPU architectures. Our two companies already share customers and we expect this to grow rapidly on RISC-V as well as other platforms. Enabling access to the SEGGER J-Link functionality from within the UltraSoC environment makes perfect sense.”

Embedded analytics platform for design and debug of real-time systems

December 6, 2017 By Aimee Kalnoskas Leave a Comment

Embedded software systems – which are at the heart of a variety of electronic products from lightweight IoT sensors to high-performance computing (HPC) platforms – are prone to sporadic errors that can be hard to spot and virtually impossible to predict or to prevent from reoccurring. At the same time, traditional chip design requires the use of debug tools to ensure the chip is ready for production. However, traditional hardware debug tools do nothing to spot nor to prevent changes or problems in the completed system in the field: these can significantly affect performance or power, impacting security and safety amongst other things.

UltraSoC embedded analytics technology provider, and Percepio AB, specialists in software tracing tools for real-time operating systems, announced a partnership to produce a comprehensive solution for designing and debugging complete, robust real-time systems.

Combining Percepio’s Tracealyzer tools to provide insight into real-time behaviors in RTOS-based (real-time operating system) embedded software, with UltraSoC’s hardware-based universal monitoring and analytics platform, the partnership allows embedded development teams to achieve enhanced system performance, as well as significant benefits in predictability, power, security and safety – plus reduced time-to-market and system development costs.

Through this partnership, the Percepio and UltraSoC embedded debug tools are able to communicate and share essential information in real-time to ensure system-wide monitoring, effectively guaranteeing maximum performance and reliability.

“UltraSoC’s universal semiconductor debug, monitoring and analytics platform is an ideal complement for our Tracealyzer visualizations,” commented Johan Kraft, CEO and founder of Percepio. “By combining our tools and offering something the industry has never seen, there are significant opportunities available to both companies.”

UltraSoC CEO Rupert Baines added: “I’m excited to be able to address additional customer needs with Percepio’s ground-breaking Tracealyzer tools. By having an out-of-the box offering that combines both software and hardware analytics that work perfectly together, the time-to-market and development cost savings we can both offer our customers will be significant.”

Percepio is widely used by designers using FreeRTOS, RTLinux and VxWorks, amongst other environments. UltraSoC’s analytics IP is designed to be used across any hardware platform, providing semiconductor designers with embedded analytics and intelligence in hardware debug. Bringing these two toolsets together ensures system designers benefit from an integrated embedded analytics solution. Synchronizing Percepio’s Tracealyzer with UltraSoC’s IP modules gives system designers an unparalleled insight into their embedded hardware and software.

Percepio’s Tracealyzer embedded software debug tool offers unprecedented levels of insight into the run-time behavior of complex multi-threaded RTOS (Real Time Operating systems) or Linux-based software systems, allowing for improved development productivity, reduced time-to-market and better software quality. Tracealyzer is already used by companies with very demanding applications in industrial, robotics and drilling industries, amongst others.

UltraSoC’s embedded semiconductor IP simplifies development of such complex and powerful devices – even in heterogeneous multi-core systems. UltraSoC’s embedded analytic features support developers of systems in a broad range of applications, such as: safety and security in the automotive industry, where the move towards autonomous vehicles is creating unprecedented change and risk; optimization in big data applications, from search to data centers; and cybersecurity, including for the Internet of Things.

Debug and trace technology added to open-source RISC-V CPU platform

September 7, 2017 By Aimee Kalnoskas 1 Comment

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC’s embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC’s debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.

The DesignShare concept enables an entirely new range of applications. Companies like SiFive, UltraSoC and other ecosystem partners have developed efficient, pre-integrated solutions to lower the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization. The partnership between SiFive, originator of the industry’s first open-source chip platform, and UltraSoC, the industry leader in vendor-neutral on-chip debug and analytics tools, significantly strengthens the ecosystem surrounding RISC-V, the open source processor specification which is often dubbed “the Linux of the semiconductor industry”.

“SiFive was founded with the mission to disrupt the semiconductor industry by leveling the playing field for anyone who wants to develop custom silicon,” said Naveed Sherwani, CEO of SiFive. “The DesignShare ecosystem enables aspiring system designers with the tools they need when designing their SoC. We’re thrilled to welcome UltraSoC to the DesignShare ecosystem and look forward to seeing the innovations our collaboration brings to the market.”

UltraSoC’s IP simplifies the development of systems on chip (SoCs) and provides embedded analytics features that enable chip makers to cut development costs significantly and increase the profitability of their projects. The company has taken a leading role in producing a specification for RISC-V processor trace functionality, which UltraSoC and SiFive intend to work together with the RISC-V Foundation to incorporate fully into the RISC-V standard. Trace is a fundamental requirement for developers working with any processor architecture, allowing engineers to view the behavior of their programs in detail, isolating bugs and identifying areas for improvement. UltraSoC and SiFive IP fully supports this recently released trace specification.