The mobile industry processor interface (MIPI) improved inter-integrated circuit (I3C) host controller interface (HCI) provides a scalable, low-power, medium-speed, two-wire I3C utility and control bus interface for connecting peripheral devices to application processors in smartphones, computers, Internet of Things (IoT) devices, automotive systems, and similar applications.
MIPI I3C HCI supports faster design times for applications based on the I3C interface (Figure 1). Instead of spending time developing product-specific drivers, device designers can use generic I3C drivers that are portable across hardware platforms. The standardized interface provided by MIPI I3C HCI implements the core I3C interface requirements and allows vendor- and application-specific innovations. In addition, the I3C and I3C HCI specifications are backward compatible with the legacy I2C interface.
Version 1.1 (v1.1) completed the harmonization of the HCI specification with the latest I3C specifications. It enhanced some existing features and added new ones. According to the MIPI Alliance, two key features in v1.1 are the addition of group addressing and the enabling of defining bytes on the common command codes (CCCs).
Using group addressing, developers can assign a multicast address to multiple I3C peripheral devices. Prior to group addressing, developers had to implement one-to-one mapping of addresses to device types. Group addressing is expected to be particularly useful for processes like firmware updates where a controller can send the same firmware to multiple devices simultaneously.
Enabling defining bytes on the CCC gives developers more flexibility when creating new CCCs or augmenting existing CCCs already defined in MIPI I3C. That supports basic control over the operation of the target I3C device or functions.
More v1.1 enhancements
Improved operation in direct memory access (DMA) mode is another enhancement in v1.1. DMA mode relies on internal DMA engines and a system bus that provides DMA capability to enable autonomous host controller-initiated DMA requests to implement transactions without a separate software action.
Additional enhancements include:
- Command flows like the RSTACT CCC for configurable target resets.
- Using the SETAASA CCC to assign all static addresses as dynamic addresses.
- More options for recovering the I3C bus from a stuck serial data (SDA) line on a target device or after a controller reset.
- Enabling variable length data for read transfers. This can be especially useful when the response data is shorter than the requested data.
- Ability to detect and report I3C bus stall or timeout conditions when a sequence of multiple transfer commands in continuous framing is interrupted, and the controller must drive a STOP command before the last transfer command.
While v2.0 is still under development, MIPI has released v1.2 as an intermediate update to HCI that supports the latest updates to I3C. HCI v1.2 includes a group of ‘optional normative’ features to address needed features and close gaps identified in v1.1. Some of the features include:
- Standby controller
- More flexible scheduled transfer commands
- Early termination of high data rate (HDR) transfers.
- Streaming in-band interrupts (IBIs) with no defined end of payload data.
- Improved dead bus recovery.
I3C HCI driver for Linux
MIPI recently released an I3C HCI driver for Linux that has been available in the source distribution since the release of the Linux 5.11 kernel. Benefits of the Linux driver standardized interface include:
- Ability to use a common driver to detect, configure, and present I3C targets to an application.
- Controller configuration using common register definitions.
- Common data structures for transfer commands and responses.
- MIPI system software trace (SyS-T) has been added to the Linux kernel to provide a standard format for transmitting software trace and debug information to debug and test systems (DTSs) (Figure 2).
MIPI I3C HCI supports faster design times for applications based on the I3C interface. It provides a scalable, low-power, medium-speed, two-wire I3C utility and control bus interface for connecting peripheral devices to application processors in a wide range of applications. It has recently been added to the Linux kernel.
Enhanced I3C Host Controller Interface, MIPI Alliance
Frequently Asked Questions (FAQ) for MIPI I3C HCI v1.2, MIPI Alliance
I3C HCI Host Controller, Arasan
MIPI I3C HCI v1.2, MIPI Alliance
MIPI SyS-T Is Now Part of Linux Kernel, MIPI Alliance