Faraday Technology Corporation, a leading ASIC design service and IP provider, and United Microelectronics Corporation, a leading global semiconductor foundry, today announced the availability of Faraday’s PowerSlash™ fundamental IP on UMC’s 55nm ultra-low-power process (55ULP) technology. The combination of PowerSlash™ with UMC’s process technology, both engineered for very low-power wireless applications, is optimized to serve wireless Internet of Things (IoT) applications that require extended battery life.
“In the realm of IoT applications, low-power consumption and high-performance are often considered as trade-offs,” said Remi Yu, Vice President of Marketing and Investment at Faraday Technology. “With the combination of UMC’s 55ULP ultra low-power technology and Faraday PowerSlash IP Turbo Mode capability, chip designers now have a choice to have the advantages of both worlds — longer battery life and better performance tailored for IoT use scenarios. It marks another success story of the partnership by UMC and Faraday.”
Fully leveraging UMC’s 55ULP advantage, Faraday’s PowerSlash IP works under extended power supply voltages that range from 0.81V to 1.32V. It includes multi-Vt libraries, fine-power granularity memory compilers and a comprehensive power management kit. In addition, the newly featured Turbo Mode effectively shifts the performance curve, helping MCU cores to achieve 2x performance or reduce dynamic power by 40% at nominal clock rates.
“IoT chip designers demand streamlined solutions with energy-efficient features,” said Yanan Mou, senior director of the IP Development & Design Support division at UMC. “UMC possesses the foundry industry’s most robust IoT-specific 55nm technology platform, supported by highly comprehensive IP resources to address the ‘always on’ ultra-low power requirements of IoT products. With the availability of Faraday’s PowerSlash IP on our 55ULP, customers have access to one of the industry’s most comprehensive platforms dedicated to the unique needs of IoT products.”
The PowerSlash IP, combined with Faraday’s existing low-power design methodology, SoC ultra-low power control unit, and FIE3200 FPGA platform, can be utilized for low-power IC designs either during the front-end design phase or in back-end implementation. UMC’s 55ULP technology can support both lower operating voltage and sub-pA device leakage, making the process ideal for button-cell battery applications. The synergy created by both Faraday and UMC’s ultra-low power technologies sets new benchmarks for ultra-low power IC design platforms.
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