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64-bit

ROS now supports 64-bit processor cores

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SEGGER has announced that its embOS real-time operating system now supports 64-bit processor cores.

Today, most IoT implementations and other sophisticated embedded applications rely on 32-bit CPUs. In the very near future, however, they will start migrating to higher performance 64-bit CPUs. This is because the latest generation of SoCs and FPGAs with advanced peripherals (like SuperSpeed USB and Gigabit Ethernet) tend to also come with powerful 64-bit CPU cores incorporated. Such peripherals are usually not available to the 32-bit core devices currently deployed.

With embOS, users can now easily upgrade to 64-bit systems while continuing to run the same application software as deployed to their current 32-bit platforms. This will ensure that the same deterministic real-time behavior is maintained while enabling even higher speeds to be delivered.

In many cases, the small footprint of embOS enables the use of 64-bit cores with just the on-chip RAM and cache memory. This eliminates the need for the inclusion of external RAM. The number of components is consequently lowered, thereby reducing both the complexity and cost of the end product.

embOS is a commercial RTOS that makes every bite count. It is available for use across all-silicon manufacturers’ platforms and directly supported by the experts who wrote the code.

SoM sports hardened 64-bit, multicore RISC-V MPU subsystem

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Sundance has launched PolarBerry, the first production and deployment-ready SoM with a hardened 64 bit, multicore real-time, Linux-capable RISC-V MPU subsystem to deliver an unparalleled combination of defense-grade security, low power consumption, and thermal efficiency for embedded systems development.

With Microchip Technology Inc.’s PolarFire SoC field-programmable gate array (FPGA) at its heart, providing a deterministic, coherent 64-bit RISC-V CPU cluster and a deterministic L2 memory subsystem enabling the implementation of secure Linux and real-time applications, PolarBerry is ideally suited to the development of embedded computing and real-time applications based on RISC-V processors as an alternative to ARM. Typical applications will be found in the defense/mil-aero, AI/ML, communications, automotive, industrial automation, and imaging markets as well as the Internet of Things.

PolarBerry’s compute engine delivers up to 50% lower power than alternative FPGAs, 250k logic elements (LEs), and features four high-speed, low-power transceivers from 250Mbps to 12.7Gbps. The PolarFire SoC FPGA’s power consumption is 12W maximum and power provided directly from the PolarBerry SoM to enable embedded solutions.

The PolarBerry SoM offers all the important attributes for strong SoC/FPGA design security including anti-cloning protection, device-level anti-tamper features, bitstream protection, key management, FPGA hardware access control, secure boot and physical memory protection (PMP) as well as supply chain assurance. It also features a 40 pin Raspberry Pi (RPI) interface to allow standalone operation and rapid application development by providing up to 26 GPIOs, 20 of which can be assigned to SPI, UART, CAN, or other interfaces. All RPI signals are 3.3V logic. Associated onboard PolarBerry SoM peripherals include 4GB of 32-bit wide DDR4 memory, 128MB SPI Serial NOR FLASH for storing the boot image, and programmable clocks to provide flexible clocking to the FPGA and high-speed transceivers. There is also an RJ45 Ethernet socket with a 100/1000Base-T interface, two CAN 2.0 physical layers, a JTAG interface for programming, and 4GB of eMMC non-volatile storage. Samtec connectors provide high-speed communication to a carrier board for powerful peripheral customization. The power consumption of the module is 16W with the power it can be applied via a PRI interface or carrier board.

The PolarBerry SoM measures just 55mm by 85mm and has an operational temperature range of 0°C and +70°C. It can also be installed on Sundance’s PCIe SoM carrier to provide access to an FMC and additional interfaces.

PolarBerry is part of Microchip Technology’s “Get Launched!” campaign and has been released now for early adaptors at a price of US$995 for delivery in January 2021. For more information about Microchip Technology’s “Get Launched!” campaign, visit https://www.crowdsupply.com/microchip/get-launched.

High-performance 64-bit ARC processor IP boosts performance by 3X

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Synopsys announced the new DesignWare ARC HS5x and HS6x processor IP families for high-performance embedded applications. The 32-bit ARC HS5x and 64-bit HS6x processors, available in single-core and multicore versions, are implementations of a new superscalar ARCv3 Instruction Set Architecture (ISA) and deliver up to 8750 DMIPS per core in 16-nm process technologies under typical conditions, making them the highest performance ARC processors to date.

64-bit ARC processorThe multicore versions of the new ARC HS processors include an innovative interconnect fabric that links up to 12 cores and supports interfaces for up to 16 hardware accelerators, all while maintaining coherency among the cores.  The processors can be configured for real-time operation or with an advanced memory management unit (MMU) that supports symmetric multiprocessing (SMP) Linux and other high-end operating systems. To accelerate software development, the ARC HS5x and HS6x processors are supported by the ARC MetaWare Development Toolkit that generates highly efficient code. The new ARC HS processors are designed to meet the power, performance, and area requirements of a broad range of high-end embedded applications including solid-state drives (SSDs), automotive control & infotainment, wireless baseband, wireless control, and home networking.

The ARC HS5x and ARC HS6x processors are based on the new ARCv3 ISA that implements a full range of 32-bit and 64-bit instructions.  These processors feature a high-speed 10-stage, dual-issue pipeline that offers increased utilization of functional units with a limited increase in power and area.  The HS5x processors feature a 32-bit pipeline that can execute all ARCv3 32-bit instructions, while the HS6x processors feature a full 64-bit pipeline and register file that can execute both 32-bit and 64-bit instructions.  In addition, the ARC HS6x supports 64-bit virtual and 52-bit physical address spaces to enable direct addressing of current and future large memories, as well as 128-bit loads and stores for efficient data movement.

Multicore versions of both the ARC HS5x and HS6x processors include an advanced high-bandwidth intra-processor interconnect that has been designed to ease development and timing closure with asynchronous clocking and up to 800 GB/s internal aggregate bandwidth.  To further simplify physical design and timing closure in multicore configurations, each core can reside in its own power domain and have an asynchronous clock relationship with the other cores.  A new 128-bit vector floating point unit supports F16, F32, and F64 operations with a 2-cycle accumulation latency. Like all ARC processors, the HS5x and HS6x processors are highly configurable and implement ARC Processor EXtension (APEX) technology that enables the support of custom instructions to meet the unique performance, power, and area requirements of each target application.

The HS5x and HS6x processors are supported by Synopsys’ ARC MetaWare Development Toolkit that includes an advanced C/C++ compiler optimized for the processors’ superscalar architecture, a multicore debugger to debug and profile code and a fast instruction set simulator (ISS) for pre-hardware software development. A cycle-accurate simulator is also available for design optimization and verification. Open-source software support for the processors includes the Zephyr real-time operating system, an optimized Linux kernel, the GNU Compiler Collection (GCC), GNU Debugger (GDB), and the associated GNU programming utilities (binutils). Additional hardware and software tools are available from third-party partners, giving developers the flexibility to choose the best and most familiar tools for their design project.

The DesignWare ARC HS5x and HS6x processors are scheduled to be available in Q3, 2020. The new processors will include the ARC HS56, HS57D, HS58, HS66, HS68 and multicore versions (HS56MP, HS57DMP, HS58MP, HS66MP, HS68MP) of each.

Trace visualization tool now supports On Time RTOS-32

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Trace visualization toolPercepio announces that Tracealyzer 4 support for On-Time RTOS-32, in addition to the already supported Amazon FreeRTOS, Keil RTX5, Micrium µC/OS-III and SafeRTOS/OpenRTOS.

“Tracealyzer 4 is a massive improvement over previous versions. We have collaborated with On Time for more than five years and we are excited to now bring the next generation in RTOS tracing to On Time RTOS-32 users,” says Dr. Johan Kraft, CEO of Percepio.

This is the most comprehensive update of Tracealyzer since the first Tracealyzer support for On-Time RTOS-32 was released in 2012, and developers using RTOS-32 can now benefit from the many new features in Tracealyzer 4, such as a completely redesigned, modern GUI and user-defined analysis which allows you to visualize important intervals and states, much like a logic analyzer for software.

The integration with On Time RTOS-32 has not changed, so existing customers can easily upgrade by contacting sales@percepio.com or their nearest Percepio distributor.

The support for On-Time RTOS-32 was introduced in Tracealyzer 4.2.3, available for download and evaluation at percepio.com.

High-speed I/O processors sport 64-bit time-predictable and energy efficient cores

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Kalray announced that it will launch the third-generation of its high-performance MPPA processor: the MPPA3 Coolidge. With the success of its second-generation MPPA2-256 Bostan processor, selected by numerous automotive and aeronautic OEMs and Tier1’s, Kalray has taken its unique manycore technology to the next level in terms of performance.

The third-generation of the MPPA will be available for critical embedded applications, like autonomous vehicles, aeronautics, medical devices, robotics and drones. The chip will bring unique data fusion capabilities and will be especially efficient for compute-heavy processing, like deep learning and computer vision.

The MPPA3 Coolidge will be produced with 16nm FinFet technology and is designed for ASIL B safety functionality. It will be comprised of 80 or 160, Kalray 64-bit time predictable and energy efficient cores and, in addition to the cores themselves, will boast 80 or 160 complimentary co-processors used for the acceleration of computer vision and deep learning. The Coolidge will run at 1.2 GHz of core frequency using less than 20W of power. This superior ratio will be the key to making Coolidge work for high performance embedded applications. Coolidge performances are expected to reach up to 5 Tera FLOPS and 9 TOPS.

The MPPA Coolidge will be compatible with multiple interfaces – PCIe, Ethernet, DDR, CAN, USB and others. It will also contain security and safety blocks to keep the processor running safely and protect systems against cyber-attack.

The MPPA Coolidge will be commercially available in mid-2018. Kalray is currently working with various customers to put the Coolidge at the heart of newly developed critical embedded applications.

In addition to its industry-leading power efficiency, the architecture of Coolidge will offer numerous other major advantages for customers: its massive parallelization will allow multiple applications to run in parallel at high performances, and mixing application criticality and its predictable architecture will allow applications to be predictable.

The Internal Processor Bus: data, address, and control bus

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A bus is a pathway for digital signals to rapidly move data. There are three internal buses associated with processors: the data bus, address bus, and control bus. Together, these three make up the “system bus.” The system bus is an internal bus, intended to connect the processor with internal hardware devices, and is also called the “local” bus, Front Side Bus, or is sometimes loosely referred to as the “memory bus.”

Data moving in and out of the data bus is bi-directional, since the processor reads and writes data, however, the others are uni-directional, since the processor always determines when and what it will read from or write to. The address bus carries addressing signals from the processor to memory, I/O (or peripherals), and other addressable devices around the processor. Control signals move out of the processor, but not in to it.

Figure 1: Internal system bus. By W Nowicki – Own work, based on a diagram in The Essentials of Computer Organization and Architecture By Linda Null, Julia Lobur. CC BY-SA 3.0

The data bus “width” of an MCU is typically 8-, 16-, 32- or 64-bits, although MCUs of just a 4-bit data bus or greater than 64-bit width are possible. The width of the data bus reflects the maximum amount of data that can be processed and delivered at one time.  A 64-bit processor has a 64-bit data bus and can communicate 64-bits of data at a time, and whether the data is read or written is determined by the control bus. The physical location of the data in memory is carried by the address bus. An internal hardware component, having received the address from the address bus and about to receive the data, enables a buffer to allow the flow of signals to or from the location that was designated by the address bus. The address bus carries only the information regarding the address, and is synchronized with the data bus to accomplish read/write tasks from the processor. The address bus is only as wide as is necessary to address all memory in the system.

Other communication buses also communicate with the processor but are external to the system, such as Universal Serial Bus, RS-232, Controller Area Network (CAN), eSATA, and others. External peripherals may be set up to use the internal bus, and this was common with computers that used “expansion cards” to connect products to the internal bus. However, with one card per device this became untenable for the long term, and other bus communication systems such as USB were developed.

A system bus can be “extended” to communicate with other computers via a chassis called a backplane. Internal buses have very rapid throughput and low latency. Several computers can be rack-mounted in a single backplane for very fast communication between computers.

64-bit MCUs in 4 mm x 4 mm packages offer 256 KB Flash

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The new PIC24 “GA7” family of microcontrollers (MCU) is now available from Microchip Technology Inc.  As the lowest-cost 256 KB Flash memory 16-bit MCUs available today, these PIC24 devices enable extremely cost-effective designs for Internet of Things (IoT) sensor nodes, portable medical devices and industrial control applications. 

The PIC24 “GA7” family enables developers to cut power consumption, cost, and space. The devices offer low-power modes including multiple sleep modes, down to 190 nA, to greatly decrease power consumption for extended battery life in portable applications at a fraction of the cost of previous solutions. The new devices also offer up to 256 KB Flash and 16 KB RAM and are available in 28, 44 and 48 pin count package options, some as small as 4 x 4mm.

Products in the PIC24 “GA7” family support Core Independent Peripherals (CIPs) such as configurable logic cell (CLC), Multi-output Capture Compare Pulse Width Modulation module (MCCP) and Direct Memory Access (DMA), which allow developers to accomplish tasks in hardware while freeing up the central processing unit (CPU) to do other tasks or to go to sleep. The new microcontrollers also features a robust peripheral set including 12-bit, 200 ksps Analog to Digital Converter (ADC), up to seven timers and two Universal Asynchronous Receiver/Transmitters (UARTs).

The new PIC24 “GA7” family is supported by the Explorer 16/32 Development Board ecosystem (DM240001-2) as well as the new PIC24FJ256GA705 Plug-In Module (MA240039) which plugs into the Explorer 16/32 Board for easy evaluation and development. Speed up development by leveraging the “GA7” family’s compatibility with Microchip’s established software development platforms including MPLAB® Code Configurator (MCC), MPLAB X IDE and XC16 Compiler.

The PIC24 ”GA7” devices are also supported by Microchip’s MPLAB Xpress Cloud-Based IDE, which is an online development environment containing the most popular features of MPLAB X IDE. MPLAB Xpress incorporates the latest version of MPLAB Code Configurator, which enables users to automatically generate initialization and application C code using a graphical interface and pin map. Best of all, MPLAB Xpress IDE is free, and can be accessed from any Internet-connected computer, anywhere in the world.

The PIC24 “GA7” family is available in 64KB, 128KB and 256KB Flash variants with 28-pin, 44-pin and 48-pin packaging options. All devices are currently available with volume pricing starting at $0.80 USD.

 

Top microcontroller threads on EDAboard.com – July

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(editor’s note: Intrigued by the problem? Have a question or optional solution? Then click the “Read more” link and follow the conversation on EDAboard.com or log in to EDAboard and participate in the microcontroller forum thread.)

Using a PIC to generate square wave sweep tones – I am trying to design a controller for a 12V siren (for an alarm system). The controller will output square waves from the PIC using 2 outputs that are 180-deg out of phase with each other (inverted). Both outputs feed through an H-BRIDGE amp to an 8Ω speaker (to get maximum volume). I do NOT need sine waves, sawtooth, etc. I only need to output square waves. Frequency range will be as low as 300Hz to as high as 2650Hz. Read more

MikroC project check – I’ve made a simple controller for a 3-stage elevator. The main problem is that when testing on Proteus it works great and even on a real board. But sometimes there are errors such as not responding to the emergency push button (which its normally closed) or converting the input pins to outputs and not responding to the limit switch. Read more

mikroC

P10 led connection explanation – I have interfaced my own LED matrix with PIC, 8051,  and AVR microncontrollers. Now I want to interface it with a P10 LED module. The pins are shown here. Need help programming. Read more

p10_display_pinout (1) p10_display_32x16_red_back

PIC18f4520 serial communication problem – I wrote a code for serial communication using PIC18F4520 and Mikroc pro. I tested it using USART terminal provided with Mikro. It is working fine. Then I tested it on another laptop with the same USART terminal. It worked fine. Both these laptop are Windows 7 32-bit systems. Then I tested it on Windows 8 with the same USART terminal software. Here it failed to work. I then tested it with another hyperterminal software on the same laptop but it didn’t work. Why? Read more

Interfacing P10 LED matrix module – I am trying to interface the P10 LED matrix display module with PIC16f1939 running at 32MHz, MPLABx and HI TECH C Compiler. To send the data to the display, I am using a software SPI routine. However I don’t see anything on my display; it’s just blank. Read more

Problem with call function in MikroC – I am using an Atmega8A, a 16 M crystal, and a MikroC for AVR IDE. I have a function I want to call about 150 times continuously. But my code does not work. If I call it less than 30 times, it will work. Why? Read more

call function problem

Is PIC16F505 a good choice? – I want to use a microcontroller for my design for checking input and output current and voltages, triggering FETs, and battery charge monitoring. I have chosen the PIC16F505. Will this be a good choice for my application? Read more

Need help with PIC16F877A using Pickit3 – I’m trying to connect a PIC16F877A to program it in MPLAB X IDE, but I’m getting an error about the target device ID. Below is my breadboard. Read more

pickit 3 error

Illegal conversion between types – I am trying to reuse a code for different pins in the PIC16f877a. For that, I have uses the structure concept in C. I haven’t completed my program. I compiled it for any syntax errors and I got this error: [illegal conversion between types int -> struct DHT11]. Read more

PIC microcontroller port pins changing – I want to interface both SPI and I2C devices in the same PIC microcontroller. How can I  change the pins of the I2C? Read more

Intel Quark Microcontroller: x86 right for IoT

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by Bill Giovino, Mouser Electronics

It seems that every semiconductor company has a microcontroller solution for the Internet of Things (IoT) today. We are seeing specs for low power, high performance, and high integration microcontrollers from the usual core suppliers. But when Intel announced that it was re-entering the microcontroller business with a 32-bit x86 MCU for the Internet of Things, it was like Thor picking up his hammer to take on the competition again.

Intel’s new IoT microcontroller product line is the Intel Quark microcontroller family, and it emulates the small yet highly powerful subatomic particle it is named after. With the Intel Quark microcontroller, Intel has rolled out its groundbreaking 32-bit i486 architecture – that’s right, the same CPU architecture used to run desktop PCs is now powering little embedded IoT applications.

The x86-based Intel Quark microcontroller D2000
The latest Intel Quark brand in the product line is the Intel Quark microcontroller D2000. It starts with a single-threaded i486 register-based core, then adds the six Intel Pentium™ optimization instructions, resulting in a 32-bit Pentium-compatible instruction set architecture (ISA) without the SIMD or x87 floating point support. The Pentium instruction set actually has some surprising features that make it applicable to embedded code, such as a single-cycle 32×32 multiply as well as some bit test instructions. There are also some unusually complex logic instructions such as a “Bit-wise Logical AND and NOT“.

IntelQuarkD2000-Fig1
Figure 1: Intel Quark Microcontroller D2000 Block Diagram (Source: Intel)

The instruction set has a flexible opcode size, some instructions are 32-bits long, while stack instructions need just a single byte. This flexibility helps compilers generate more compact code.

The Pentium’s mature ecosystem
By choosing a Pentium-compatible instruction set, Intel has made the Intel Quark processor core compatible with the large number of Pentium compilers out there, giving it additional optimizations from a code development ecosystem even more mature than ARM. This also allows access to a vast library of Pentium-ISA compatible code which can be easily ported to the Intel Quark microcontroller. Thread-X and Zephyr are two popular small footprint x86 RTOS packages that can fit easily in the Intel Quark microcontroller. There are a number of legacy RTOSs available that were tested, verified, and made solid 30 years ago that can run flawlessly.

The Intel Quark processor core includes memory block protection, an internal AHB bus interface, a JTAG port, a wakeup controller, and an interrupt control unit (ICU).

When looking at the low power figures of the Intel Quark microcontroller D2000, the numbers are surprising. Running the device at 32MHz at 3.3V, the draw is only 8mA. This results in a 32-bit Pentium-ISA core with the power draw of some 8-bit microcontrollers. HALT current, with only the core and the Real Time Clock (RTC) running, results in a current draw of just 697nA. These are impressively low numbers for what is, let me remind you again, an Intel 32-bit embedded Pentium microcontroller.

For edge computing where the Intel Quark brand D2000 is powering a small sensor node, these power figures can result in almost two years of battery life off a 9V lithium battery.

IntelQuarkD2000DevBoard-Fig2
Figure 2: Intel Quark brand D2000 Developer Board with Arduino Headers (source: Intel)

It is tied to 32KBytes of Flash program memory and 8KBytes of SRAM. An additional 8KBytes of Flash, divided into two 4KB banks, is available for data storage. It can be treated like EPROM; alternately, it can be set to be one-time programmable (OTP) in one or both 4KB banks. For fault-tolerant IoT applications this allows for local storage of critical sensor data if, for example, the Intel Quark microcontroller determines that the wireless connection to the sensor hub has been lost and data needs to be saved locally.

The Intel Quark microcontroller D2000 sports the usual range of communication peripherals which includes a real-time clock (RTC), two 16550-compatible 2Mbaud UARTs, a master/slave I2C, and two SPIs. The analog to digital converter (ADC) on the Intel Quark microcontroller D2000 has 19 channels and can be configured to convert 12, 10, 8, or 6-bits, with speeds from 3.3Msps (6-bits) to 2.4Msps (12-bits). This is quick enough to grab plenty of atmospheric sensor data in a fast-changing environment.

The Intel Quark brand D2000 Development Board (figure 2) provides a wide variety of powerful features in a cost-effective environment. It includes a 6-axis accelerometer with 12-bit resolution, a 3-axis geomagnetic sensor, and a temperature sensor. It includes connectors for Arduino Uno-compatible shields for expanded functionality, and has a battery holder for a CR2032 coin cell capable of powering the board in low-power event driven applications for a couple of months. Application code for the Intel Quark microcontroller family is built using the Intel System Studio for Microcontrollers (Figure 3). With this code development package, developers can quickly build IoT sensor node applications including remote positional sensing, free fall detection, tilt-compensated compass, or dead reckoning applications.

IntelSystemStudio-Fig3
Figure 3: Intel System Studio for Microcontrollers Components (source: Intel)

While Intel supports various versions of their System Studio, the version for microcontrollers is free. It is based on the popular Eclipse Integrated Development Environment (IDE) and comes with two C compilers. The first is a GNU C Compiler, and the second is from Intel. Both compilers benefit from Intel Pentium architecture-specific optimizations. Besides these, there are a wide variety of 3rd party Pentium C/C++ compilers that can be easily integrated with the Eclipse IDE. RTOS-aware debugging, flash programming support, and power efficiency profiling are all features that help to optimize application code for small sensor-aware embedded applications that are typical of low power IoT sensor applications. Full hardware debugging is supported through a JTAG interface. Linux and Windows development environments are presently supported.

The Intel Quark MCU SE – taking intelligent sensor nodes to the next level
The Intel Quark Microcontroller SE takes the concept of a smart sensor node to a new level. It takes the D2000 and makes it faster by adding 8KBytes of 2-way associative L1 instruction cache. The x86 core also now has 192KBytes of Flash and 80KBytes of RAM. A flexible 8-channel DMA supports memory to memory, peripheral to memory, memory to peripheral and peripheral to peripheral transfers. Peripherals include an RTC, analog comparators, timers, PWM, UARTs, SPI, I2C, and USB ports. But the real value of the Intel Quark microcontroller SE is the new sensor subsystem and pattern-matching accelerator, each boasting impressive processing power.

IntelQuarkSE-Fig4
Figure 4: Intel Quark Microcontroller SE Block Diagram (source: Intel)

The Intel Quark microcontroller SE and intelligent sensor processing
The sensor subsystem of the Intel Quark microcontroller SE contains a standalone 32-bit ARC EM DSP core with 192KBytes of Flash. The DSP is capable of first order digital signal processing, and is meant to offload sensor processing from the x86 core. It directly interfaces a variety of peripheral resources including SPI, I2C, ADC, GPIOs, and timers that can interface to external sensors. The ARC DSP core supports fractional arithmetic, floating point, divide, square root, and more complex processing including trigonometric functions. The ARC DSP has 8KBytes of dedicated SRAM and also has a shared SRAM memory area with the x86 Pentium core for inter-processor communication.

The sensor subsystem’s ARC DSP supports intelligent data acquisition for low power applications. The DSP can be placed in a sleep state until a peripheral wakes it up to send data to be processed. The DSP wakes up, processes the data, and sends the results to the main x86 Pentium processor. For intelligent IoT sensor node applications, the sensor subsystem is a valuable feature that provides fast and accurate processing of sensor data supporting sensor fusion, data averaging, filtering, artifact rejection, and error correction.

Intelligent pattern recognition with the Intel Quark MCU SE
The new Pattern Matching Recognition Engine in the Intel Quark microcontroller SE provides machine identification of previously learned digital objects. The engine is composed of a network of parallel arithmetic units, called Neurons, which perform two types of pattern recognition. The first is called K-nearest neighbor (KNN) and the second is call radial basis function (RBF). Both allow the Intel Quark microcontroller to do some pretty impressive edge processing by performing simple pattern detection on sensor data. Upon processing a pattern, the engine returns one of three states: identification, uncertain, or unknown. Up to 32,768 identification categories can be programmed.

The pattern matching engine features 128 arithmetic units operating in parallel. In this configuration, each arithmetic unit is referred to as a neuron. The recognition time is constant, providing the added advantage in embedded systems applications of making the engine deterministic.

While this pattern matching engine can seem complicated at first glance, in reality, it supports four main operations:

  1. Load a vector knowledge base to the engine
  2. Read the vector knowledge base from the engine
  3. Load a pattern to be recognized into the engine
  4. Read the results of pattern recognition from the engine

Now, if the Pattern Matching Engine is tied into the Sensor Subsystem, the Sensor Subsystem can pass a series of vectors representing, for example, vibration, temperature, current, and audio data, to the Pattern Matching Engine which can match it against a stored dataset. If the dataset finds a hit of a pattern it has been looking for, it can trigger a wakeup event to the main x86 processor. The x86 can then make a decision to, for example, turn a switch on or off, or send an alert of the match to the main sensor hub.

This level of processing in an inexpensive chip is uncommon in microcontrollers found today, and adds significant cost-effective value to simple IoT sensor nodes. Complex processing that would normally be sent wirelessly from the node to the main sensor hub or a cloud server can be performed locally at the sensor node itself. This not only saves processing power at the sensor hub, but it also saves the node’s battery power. In an IoT node, the power draw of the node must be worth the value of the data. The more processing that can be performed at the node level, the less data needs to be transmitted wirelessly, saving power.

Conclusion
Intel has taken a big step by re-introducing their familiar x86 32-bit Pentium architecture into the microcontroller arena, but this makes sense in the IoT application field. The x86 Pentium architecture leverages a development ecosystem of compilers, debuggers, and evaluation tools that spans 30 years. While the Intel Quark microcontroller D2000 introduces an entry-level 32-bit microcontroller architecture into the marketplace, the Intel Quark microcontroller SE brings new intelligence into small cost-effective nodes, rivaling existing solutions and introducing a new era of innovation in the Internet of Things.

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Self-refresh 64 Mb DRAMs use HyperBus interface

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Pictured is a Cypress HyperRAM memory based on the low-pin-count HyperBus interface. The device serves as an expanded scratchpad memory for rendering of high-resolution graphics or calculations of data-intensive firmware algorithms in a wide array of automotive, industrial and consumer applications. (PRNewsFoto/Cypress Semiconductor Corp.)
Pictured is a Cypress HyperRAM memory based on the low-pin-count HyperBus interface. The device serves as an expanded scratchpad memory for rendering of high-resolution graphics or calculations of data-intensive firmware algorithms in a wide array of automotive, industrial and consumer applications. (PRNewsFoto/Cypress Semiconductor Corp.)

Cypress Semiconductor Corp. today announced sampling of a new high-speed, self-refresh Dynamic RAM (DRAM) based on Cypress’s low-pin-count HyperBus™ interface. The 64Mb HyperRAM™ serves as an expanded scratchpad memory for rendering of high-resolution graphics or calculations of data-intensive firmware algorithms in a wide array of automotive, industrial and consumer applications. The devices operate with a read/write bandwidth of up to 333 MBps and are available in 3V and 1.8V supply voltage ranges.

When paired with a Cypress HyperFlash™ NOR Flash memory, HyperRAM enables a simple and cost-effective solution for embedded systems where both the flash and RAM reside on the same 12-pin HyperBus. Traditional systems with an SDRAM and Dual-Quad SPI solution require upwards of 41 pins on two buses for data transactions. The HyperRAM and HyperFlash solution reduces pin count by at least 28 pins, decreasing design complexity and lowering PCB cost. HyperRAM is an ideal solution for automotive clusters and infotainment, communication equipment, industrial applications and high-performance consumer products. More information on the 64Mb HyperRAM is available athttp://www.cypress.com/hyperram.

“With the rapidly growing usage of high-resolution graphics and data-intensive applications in a wide range of systems, we see a growing need in the market for a simple, high-performance DRAM that provides external scratchpad memory for controllers with limited onboard RAM,” said Rainer Hoehler, Vice President of the Flash Business Unit at Cypress. “Our new 64Mb HyperRAM addresses this requirement with the low-pin-count HyperBus interface and its industry-leading read/write bandwidth. In addition to lower PCB cost, HyperRAM lowers MCU costs by reducing the number of pins needed compared with other DRAM solutions.”

To accelerate product design cycles, Cypress offers customers and partners a HyperBus Master Interface Controller IP Package. This controller IP helps designers add support for HyperBus to their Field-Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC) or Application-Specific Standard Product (ASSP) host controller platform. The Controller IP supports both HyperRAM, as well as HyperFlash products, and is free of charge and royalty-free.

Availability

The Cypress 64Mb HyperRAM is sampling now with production beginning in the third quarter of 2016. The devices will be available in a 24-ball, 6-mm by 8-mm ball grid array (BGA) package.

About Cypress HyperFlash Memory 

High-density (128Mb to 512Mb) HyperFlash NOR Flash memories deliver the bandwidth required for the highest-performance embedded systems found in automotive instrument clusters, automotive infotainment systems, communication systems and industrial applications. They deliver the highest read bandwidth at 333 MBps, more than four times faster than Quad SPI NOR flash, with one-third the number of pins of parallel NOR flash. More information on HyperFlash is available at www.cypress.com/hyperflash.

About Cypress HyperBus Interface

The efficient 12-pin Cypress HyperBus interface consists of an 8-pin address/data bus, a differential clock (2 signals), one chip select and a read data strobe for the controller, reducing the overall cost of a system. Memories based on the interface enable faster systems with quicker response times and rich user experiences. The Cypress HyperBus interface enables a wide range of high-performance applications, such as automotive instrument clusters, infotainment and navigation systems, handheld displays, digital cameras, projectors, factory automation systems, medical diagnostic equipment, home automation systems and home appliances. More information on Cypress’s industry-leading high-performance memory portfolio is available at www.cypress.com/memory.