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GUI development toolkit runs on 32-bit Linux MPUs

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 Microchip Technology Inc. announced a new GUI development toolkit for its portfolio of 32-bit microprocessors (MPUs) running Linux, helping designers of industrial, medical, consumer and automotive graphical displays to reduce development cost and time-to-market.

Microchip’s new Ensemble Graphics Toolkit is a free and open-source C++ GUI suite for the company’s SAMA5 and SAM9 series of Arm Cortex-A5 and ARM926EJ-S processor-based MPUs including the system-in-package and system-on-module products. The Ensemble Graphics Toolkit is optimized for Microchip’s 32-bit MPUs running the Linux operating system. By taking advantage of underlying hardware acceleration, including graphics controllers and video decoders when available, the toolkit provides a high-performance user experience on low and mid-range graphical displays up to XGA (1024 × 768 pixels) resolution.

Optimized code allows a smaller memory footprint, saving BOM cost. The efficient performance relative to other graphics solutions that rely on higher-performance cores and 3D graphical acceleration allows rich GUIs to be created for Microchip’s power-efficient MPUs. In addition, Ensemble Graphics Toolkit and Linux can be optimized for fast cold boot – with boot times of under three seconds from cold reset that is required for applications such as automotive dashboard clusters.

Microchip’s Ensemble Graphics Toolkit suite is available without licensing or royalty fees to all developers of graphical interfaces. The Ensemble Graphics Toolkit is complementary to Microchip’s bare metal/RTOS-focused MPLABÒ Harmony Graphics Suite embedded software development framework that also provides a zero-cost, royalty-free graphical user experience.

The toolkit is fully integrated with Linux4SAM, Microchip’s mainline, Long Term Support (LTS) Linux offering. In addition to supporting Microchip’s MPU families Linux4SAM contains driver support for a broad range of its components including the maXTouchÒ family of touchscreen controllers, memory devices, power management and analog devices and wired and wireless networking components and modules. Linux4SAM is regularly updated and supports all Microchip MPUs throughout product life.

Pricing

Microchip’s Ensemble Graphics Toolkit is available at no cost and royalty free for all users and includes full support from Microchip. It is based on the permissive Apache 2.0 open-source license.

Low-power GNSS IP speeds IoT modem development

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Synopsys and Nestwave today announced a collaboration to combine Nestwave’s softcore GPS navigation IP with the Synopsys DesignWare ARC IoT Communications IP Subsystem for a complete low-power global navigation satellite systems (GNSS) solution for integration into IoT modems. The collaboration will provide designers with a power-efficient, high-accuracy GPS solution for battery-operated devices without the additional cost of a dedicated GNSS chip. The joint solution will be presented at the Synopsys ARC Processor Virtual Summit on Wednesday, September 9, 2020.

The ARC IoT Communications IP Subsystem is an integrated hardware and software solution that combines Synopsys’ DSP-enhanced ARC EM9D processor, hardware accelerators, dedicated peripherals, and RF interface to deliver efficient DSP performance for ultra-low bandwidth IoT applications. Nestwave’s GNSS solution takes advantage of the ARC EM9D processor’s efficient DSP capabilities and ability to add dedicated hardware accelerators or custom instructions using APEX technology to reduce frequency requirements, giving customers additional performance bandwidth. The ARC EM9D processor is supported by the MetaWare Toolkit, which includes a rich library of DSP functions, allowing software engineers to rapidly implement algorithms from standard DSP building blocks.

Nestwave has developed an ultra-low power, advanced global navigation satellite systems (GNSS) solution for use in IoT applications. When integrated with an IoT modem such as NB-IoT, Cat M1, LoRa or Sigfox, the solution offers low-cost geolocation for emerging applications such as asset tracking, smart factories, and smart cities, without the need for an external GNSS chip.

New CPU cards speed real-time ray tracing, AI training

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Quadro Turing architecture MXM GPU moduleGPGPU and edge AI solution provider Aetina Corp. announces the newest Quadro Turing architecture MXM GPU module. Quadro RTX provides real-time ray tracing and AI training acceleration, sending the most professional GPU to achieve the highest quality and reliability standards. Quadro, NVIDIA graphics cards intended for workstations, running professional computer-aided design (CAD), computer-generated imagery (CGI), digital content creation (DCC) applications, scientific calculations, and machine learning.

Aetina released three Quadro MXM modules, including M3T1000-PN based on Quadro T1000, M3T3000-QN based on Quadro RTX3000, and M3T5000-WN based on Quadro RTX5000. With up to 3,072 CUDA cores and 9.4 TFLOPS performance can achieve almost every needed from industrial and professional graphics design fields. Meanwhile, there are up to four display ports, support HDR video by up to 8K at 60Hz resolution, which sent the users not only fabulous visual working experience but also meets up the work requests of accurate data analysis.

This Quadro MXM series based on Turing architecture, the perfect high-performance visual computing in the data center. Particularly for NVIDIA RTX Turing, supports real-time ray tracing, showing realistic lighting, shadowing, and reflection, and immediately performs a movie-grade rendering. RTX Turing GPUs feature new advanced shading technologies that are more powerful and flexible than the previous version.

Quadro RTX Turing supports deep learning super-sampling (DLSS) technology, catch up trends with AI functions. With Tensor cores, taking 10X speedups in AI training with TF32 and 2.5X boosts for HPC with FP64, providing a revolutionary AI training and inferencing power and graphics computing abilities.

All Quadro MXM modules are available.

DSP development software works with FPGAs

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DSP development softwareDSP development softwareMenta today announced the release of the new Menta Origami Programmer 2020.1, an enhanced version of the company’s innovative, robust and easy-to-use programming software.

The new Menta Origami Programmer 2020.1 can be demonstrated through webEx and evaluation licenses delivered through the Menta Starter Pack (MSP).

Also announced at Design Automation Conference (DAC) 2020, the virtual experience conference, is Menta’s Adaptive Digital Signal Processor (DSP) solution. The newly introduced Adaptive DSP solution can be inferred automatically using Menta Origami tool suite within the user’s embedded FPGA (eFPGA).

The Adaptive Menta DSP solution will allow users to implement the ideal DSP architecture within the eFPGA IP that better suits the hardware requirement. Operand size can be chosen for both the multiplier and the arithmetic logic unit (ALU).

The DSP block operating modes are programmable through the bitstream. It can dynamically be reconfigurable, and its behavior can be controlled at clock cycle level.

A Menta FIR generator empowers users to generate RTL code of an optimized FIR using Menta patented DSP FIR engine. The range of the FIR supported can be set between 4 and 512 taps, allowing users to define the number of DSP to use within their architecture as well as the data bus, and the ALU size, helping users meet frequency, area and latency goals.

DSP configuration is made easy through Origami Designer eFPGA IP software graphical interface and the adaptive DSP is automatically inferred by Origami Programmer synthesis.

Visitors to DAC 2020, a virtual experience, can learn more about Menta’s technological innovations at www.menta-efpga.com. A whitepaper about DSP is available upon request at: https://dac2020.pathable.co/organizations/5FbETpQuPPHBaRFcR.

 

All-optical HDMI 2.1 ICs feature low power consumption/idle mode for max energy efficiency

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HDMI 2.1 ICsArtilux unveiled its Connect Series, the world’s first fully compliant all-optical HDMI 2.1 IC solutions based on CMOS technology. The data transfer speed, handshakes and protocols are compliant from 1.4 all the way to 2.1. with HDP, DDC, HDCP, CEC, and ARC/eARC all enabled in the speed of light.
Artilux has demonstrated the world’s first all-optical and fully HDMI 2.1 compliant IC solutions with 300m fiber cable delivering HDMI 2.1 signals from the source generator to 8K TV.

Upcoming gaming consoles like Playstation 5 and Xbox Series X along with content-rich industries like entertainment and eSport are the main driving force for delivering real-time rich content to 4K and 8K TVs. The long reach, lightweight and flexible optical cable is becoming an essential need for not only centralized multi-display systems used in commercial buildings, but also consumer-grade large video and audio data transfer by offering the most cost-effective and energy-efficient way to fulfill these needs.

Artilux’s all-optical HDMI 2.1 IC solution supports multi-speed ranging from the latest 2.1 standards to backward compatible with 2.0 and 1.4. The complex security and control handshake protocols are all realized in the speed of the light. To maximize energy efficiency, it features a strong emphasis on achieving ultra-low power consumption with idle mode supported. This all-in-one-package aims to trigger the next wave of data communication to not only bridging the bandwidth chasm between conventional B2B and B2C market demands but also making the once expensive optical communication affordable for consumer usages.

 

MPUs include vision-optimized AI accelerator

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RZ/V series of MPUsRenesas introduced the RZ/V series of MPUs, which includes the new DRP-AI, Renesas’ exclusive vision-optimized AI accelerator.

Industry demands for real-time, AI-based person and object recognition functionality in applications have rapidly grown, and the higher power consumption and heat generation required to power them have introduced new challenges for embedded developers.

From cameras in smart shopping cart systems that can automatically calculate totals based on cart items, to robots in factories that can safely work together with humans, to medical cameras that assist doctors in making diagnoses, the RZ/V Series will make it possible to expand the range of AI applications in embedded devices through object recognition. The first device from this new series, the RZ/V2M with DRP-AI is designed to deliver a combination of real-time AI inference and industry-leading power efficiency in embedded devices:

  • DRP-AI’s excellent power efficiency realizes power consumption as low as 4W (typ.)., eliminating the need for heat sinks and cooling fans while greatly simplifying heat dissipation measures.
  • The ISP is capable of processing 4K images at 30 frames per second and includes HDR functionality capable of handling high-contrast images, noise reduction functionality, and distortion correction functionality to substantially boost precision in AI recognition.

These features ensure the RZ/V2M’s ability to produce clear images regardless of factors such as the weather, the time of day, and the installation location.

Gen 4 PCIe switches further complex low-latency fabric topologies

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Switchtec PAX Advanced Fabric Gen 4 PCIe switch familyTo support cloud, data center and hyperscale computing that facilitates advancements in Artificial Intelligence (AI) and Machine Learning (ML), Microchip Technology Inc. released to production its Switchtec PAX Advanced Fabric Gen 4 PCIe switch family, enabling complex fabric topologies with greater scalability, lower latency, and higher performance than traditional Peripheral Component Interconnect Express (PCIe) switches.

Microchip’s Switchtec PAX PCIe family of switches provides a turnkey fabric solution and reduces time-to-market for systems requiring multi-host sharing of Single Root I/O Virtualization (SR-IOV) Non-Volatile Memory (NVMe) Solid State Drives (SSDs), Graphics Processing Units (GPUs) and other PCIe endpoints.

The Switchtec PAX devices are the industry’s lowest-power Gen 4 PCIe switches, significantly reducing total system power consumption. The Switchtec PAX family of switches is available in the following variants: 100-lane, 84-lane, 68-lane, 52-lane, 36-lane and 28-lane. Other PAX family of switches features include:

  • Advanced error containment
  • Comprehensive diagnostics and debug capabilities
  • Wide breadth of I/O interfaces
  • Integrated MIPS processor
  • Secure boot to prevent execution of unauthorized firmware through public-key cryptography.

Applications include GPU workstations, composable General Purpose GPUs (GP-GPU) fabrics, scalable multi-host systems, SR-IOV-enabled JBOFs, disaggregated systems and rack-scale architectures.

SoC handles 5G tasks on smartphones

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Dimensity 820 SoC MediaTek today announced the Dimensity 820 system-on-chip (SoC) which is optimized for premium user experiences. The Dimensity 820 delivers ultra-fast 5G speeds, and is feature-packed with MediaTek’s latest multimedia, AI and imaging innovations.

Dimensity 820 packs high performance Arm Mali G57 GPU graphics plus HyperEngine 2.0 enhancements so users can immerse themselves in the latest mobile games. Brands can embrace support for 120Hz high frame-rate displays, while leading HDR features with MediaTek MiraVision showcases the most vivid visuals in videos and streams.

MediaTek’s Dimensity 820 integrates a 5G NR (sub-6GHz) modem into this single-chip solution with MediaTek’s 5G UltraSave technologies, including exclusive 5G UltraSave Network Environment Detection and 5G UltraSave OTA Content Awareness, that altogether provides best-in-class energy efficiency. The 5G modem design also uses dynamic bandwidth part (BWP) adaption and connected mode discontinuous reception (C-DRX) power-saving technologies.

5G Carrier Aggregation (CA) technology delivers higher average speeds and a seamless handover between two 5G connection areas for the most reliable connectivity on the go. The Dimensity 820 also supports dual SIM, dual standby (DSDS) 5G technology for access to the fastest speeds and Voice over New Radio (VoNR) services on both SIMs.

The MediaTek Dimensity 820 includes:

  • Dedicated APU 3.0 (AI Processing Unit): MediaTek APU 3.0 provides more powerful AI-camera capabilities so users can capture stunning images and videos at the same time, without any quality loss.
  • HyperEngine 2.0 gaming technologies: MediaTek’s HyperEngine 2.0 provides whole smartphone enhancements for gaming. Combined with the chipset’s premium five-core GPU it delivers a superb gaming experience with optimizations that reduce network latency for smoother gameplay, support faster response times and enhance display quality. HyperEngine 2.0 also intelligently adjusts the CPU, GPU and memory resources to optimize power and performance.
  • MediaTek’s Imagiq 5.0: The flagship-class, HDR-native image signal processor (ISP) supports up to four concurrent cameras and up to 80MP sensors, giving brands more design flexibility.
  • Multi-frame 4K Video HDR: Easily to record stunning 4K HDR video even in bright and dark environments. The chip automatically captures frames at different exposures and intelligently fuses them into a single video stream, all in real-time.

The Dimensity 820 delivers best in class 5G experiences and is designed for global sub-6GHz 5G networks in Asia, North America, and Europe.

High-performance 64-bit ARC processor IP boosts performance by 3X

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Synopsys announced the new DesignWare ARC HS5x and HS6x processor IP families for high-performance embedded applications. The 32-bit ARC HS5x and 64-bit HS6x processors, available in single-core and multicore versions, are implementations of a new superscalar ARCv3 Instruction Set Architecture (ISA) and deliver up to 8750 DMIPS per core in 16-nm process technologies under typical conditions, making them the highest performance ARC processors to date.

64-bit ARC processorThe multicore versions of the new ARC HS processors include an innovative interconnect fabric that links up to 12 cores and supports interfaces for up to 16 hardware accelerators, all while maintaining coherency among the cores.  The processors can be configured for real-time operation or with an advanced memory management unit (MMU) that supports symmetric multiprocessing (SMP) Linux and other high-end operating systems. To accelerate software development, the ARC HS5x and HS6x processors are supported by the ARC MetaWare Development Toolkit that generates highly efficient code. The new ARC HS processors are designed to meet the power, performance, and area requirements of a broad range of high-end embedded applications including solid-state drives (SSDs), automotive control & infotainment, wireless baseband, wireless control, and home networking.

The ARC HS5x and ARC HS6x processors are based on the new ARCv3 ISA that implements a full range of 32-bit and 64-bit instructions.  These processors feature a high-speed 10-stage, dual-issue pipeline that offers increased utilization of functional units with a limited increase in power and area.  The HS5x processors feature a 32-bit pipeline that can execute all ARCv3 32-bit instructions, while the HS6x processors feature a full 64-bit pipeline and register file that can execute both 32-bit and 64-bit instructions.  In addition, the ARC HS6x supports 64-bit virtual and 52-bit physical address spaces to enable direct addressing of current and future large memories, as well as 128-bit loads and stores for efficient data movement.

Multicore versions of both the ARC HS5x and HS6x processors include an advanced high-bandwidth intra-processor interconnect that has been designed to ease development and timing closure with asynchronous clocking and up to 800 GB/s internal aggregate bandwidth.  To further simplify physical design and timing closure in multicore configurations, each core can reside in its own power domain and have an asynchronous clock relationship with the other cores.  A new 128-bit vector floating point unit supports F16, F32, and F64 operations with a 2-cycle accumulation latency. Like all ARC processors, the HS5x and HS6x processors are highly configurable and implement ARC Processor EXtension (APEX) technology that enables the support of custom instructions to meet the unique performance, power, and area requirements of each target application.

The HS5x and HS6x processors are supported by Synopsys’ ARC MetaWare Development Toolkit that includes an advanced C/C++ compiler optimized for the processors’ superscalar architecture, a multicore debugger to debug and profile code and a fast instruction set simulator (ISS) for pre-hardware software development. A cycle-accurate simulator is also available for design optimization and verification. Open-source software support for the processors includes the Zephyr real-time operating system, an optimized Linux kernel, the GNU Compiler Collection (GCC), GNU Debugger (GDB), and the associated GNU programming utilities (binutils). Additional hardware and software tools are available from third-party partners, giving developers the flexibility to choose the best and most familiar tools for their design project.

The DesignWare ARC HS5x and HS6x processors are scheduled to be available in Q3, 2020. The new processors will include the ARC HS56, HS57D, HS58, HS66, HS68 and multicore versions (HS56MP, HS57DMP, HS58MP, HS66MP, HS68MP) of each.

USB-powered debug probe supports trace/debug integrated with RISC-V processor cores

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J-Link PLUS PRO and ULTRA debug probeSEGGER’s products are already fully compatible with SiFive’s RISC-V processor cores, and now its J-Link probes deliver support for the new SiFive Insight debug/trace solution. This includes SiFive’s latest Nexus-based trace implementation, which enables ongoing monitoring and recording of processor instruction execution.

Via SEGGER’s highly popular J-Link PLUS, PRO and ULTRA debug probe options, plus the accompanying Ozone debugger and performance analysis software package, engineers are now able to take full advantage of SiFive Insight using on-chip trace functionality. Among the relevant features incorporated within the SEGGER debug probes is a backtracing capability (where the full execution history can be easily accessed and stepped through backwards). More advanced features, like code coverage and profiling, can also be employed – based on the execution counters processed by the J-Link software. The Ozone debug software package can subsequently generate detailed code coverage reports for software validation purposes.

“The continued support from SEGGER is a great asset to the RISC-V ecosystem, and the swift adoption of SiFive Insight is of great benefit to chip designers,” says Drew Barbier, Director of Product Marketing at SiFive. “SEGGER has supported SiFive Core IP since 2017 and continues to be a valued partner in the expansion and adoption of RISC-V for embedded solutions. We look forward to continued cooperation as the RISC-V ecosystem continues to grow and evolve.”