IAR Systems releases an update of its RISC-V build tools supporting implementation in Linux-based frameworks for automated application build and test processes. This addition further extends IAR Systems’ offering for flexible automated workflows, enabling streamlined workflows from the developer environment to Continuous Integration (CI). Thanks to the tools including the static code analysis tool C-STAT, […]
RISC-V
Utilities speed software development on complex MCU cores
Renesas Electronics Corporation announced the release of IP Utilities – a new series of solutions aimed at simplifying the development of devices incorporating Renesas intellectual property (IP). The new IP Utilities include application packages and evaluation kits, as well as expanding Renesas’ growing portfolio of leading-edge IP licenses. With the emergence of CPUs based on […]
New IDE linker program shrinks executable code by 15%
SEGGER’s Embedded Studio for RISC-V now comes with the SEGGER Linker in addition to the GNU linker. The SEGGER Linker has been developed from the ground up to create executables for Embedded Systems. For RISC-V, it shrinks the size of the resulting programs by up to 15%, shortens link time, delivers a detailed map file, […]
RISC-V for ultra-low power processing and AI on the edge
RISC-V is an exciting and rapidly-emerging technology. RISC-V is software; it is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. So far, this FAQ series has looked at how “RISC-V is growing and offers stability, scalability, and security,” the “Growing availability of tools reducing the risk of […]
RISC-V for artificial intelligence machine learning and embedded systems
Several RISC-V development efforts are targeting applications such as artificial intelligence (AI), machine learning (ML), deep learning (DL), and other high-performance embedded applications. The previous two FAQs in this series considered the capabilities of RISC-V and the near-term risks associated with the technology, and the growing availability of tools that are helping to reduce the […]
Growing availability of tools reducing risk of using RISC-V
As discussed at the end of the first FAQ in this series, “RISC-V is growing and offers stability, scalability, and security,” there is a lack of testing standards and tools for RISC-V compared with mature ISAs such as Intel and Arm. This is an area that is experiencing accelerating developments and progress. The growing availability […]
RISC-V is growing and offers stability, scalability and security
RISC-V is growing rapidly. Semico Research has projected that 62.4 billion RISC-V CPU cores will be sold in 2025. While that’s only about 6% of the overall CPU core market, RISC-V is an emerging technology that most designers should follow and become increasingly familiar with. RISC-V is becoming more commercially attractive as a result of […]
SoM sports hardened 64-bit, multicore RISC-V MPU subsystem
Sundance has launched PolarBerry, the first production and deployment-ready SoM with a hardened 64 bit, multicore real-time, Linux-capable RISC-V MPU subsystem to deliver an unparalleled combination of defense-grade security, low power consumption, and thermal efficiency for embedded systems development. With Microchip Technology Inc.’s PolarFire SoC field-programmable gate array (FPGA) at its heart, providing a deterministic, […]
Floating-point library supports embedded variant of RISC-V core
SEGGER announces a new version of the RISC-V Floating-Point Library with full support for RV32E – the embedded variant of the RISC-V core. The new library leads to a massive reduction in code size for RISC-V applications using floating point. With all arithmetic functions hand-coded in assembly language, the memory footprint of RISC-V applications using […]
Development software incorporates trace and debug for RISC-V processors
IAR Systems has extended the complete development toolchain IAR Embedded Workbench for RISC-V with support for trace as implemented by SiFive Insight, the industry’s first combined pre-integrated trace and debug solution for the freely-available, open-specification RISC-V ISA. In addition to simplifying debugging and helping enforce good coding practices, trace enables extended testing and proof of code coverage, […]
