SEGGER Embedded Studio V4.20 adds fully configurable support for debug probes using the GDB protocol. The new version can now be used with any debug probe that comes with a GDB Server. This new feature is included in all editions: ARM, Cortex-M, and RISC-V, on Windows, macOS, and Linux 32- and 64-bit platforms. Embedded Studio […]
Programmable camera incorporates convolutional neural network hardware accelerator for AI apps
M5STACK announces today its further expansion into the AIOT(AI+IOT) edge computing market with the K210 RISC-V 64 AI Camera— an innovative machine vision and machine learning programmable camera that’s competitively priced to meet the needs of a rapidly growing AI market. AI cameras help engineers quickly implement machine learning, image recognition, and speech recognition functions, and […]
Silicon reference design now available for open-source RISC-V MCU
X-FAB Silicon Foundries together with crowd-sourcing IC platform partner Efabless Corporation announced the successful first-silicon availability of the Efabless RISC-V System on Chip (SoC) reference design. This open-source semiconductor project went from design start to tape-out in less than three months using the Efabless design flow based on open-source tools. The mixed-signal SoC, called Raven, […]
Hex Five adds MultiZone security to the AdaCore software ecosystem
Hex Five Security Inc., creator of MultiZone, the first trusted execution environment for RISC-V, today joined AdaCore’s Partner Program to enable the secure execution of Ada applications on RISC-V processors. As part of the initiative, Hex Five has developed an Ada version of the MultiZone SDK and published a reference application showing how to securely […]
First secure IoT stack for RISC-V enables unlimited number of secure zones
wolfSSL and Hex Five Security, provider of MultiZone Security, the first Trusted Execution Environment for RISC-V, announce general availability of the industry-first secure IoT stack for RISC-V – a TLS 1.3 reference implementation of freeRTOS with hardware-enforced separation between OS, TCP/IP stack and root of trust. FreeRTOS is the leading real-time operating system in the market; […]
RISC-V IDE available for free download
Andes Technology Corporation, a founding member of the RISC-V Foundation announced the free download of its AndeSight Integrated Development Environment (IDE) to accelerate software development for RISC-V based SoC. AndeSight IDE is a professional IDE based on Eclipse with many useful Andes add-on features, developed and widely used over the past 13 years, which provides […]
Design verification platform for RISC-V-based AI and ML semiconductor solutions
Valtrix Technologies, an EDA company delivering Design Verification (DV) solutions for the semiconductor industry, announced that Esperanto Technologies has selected Valtrix’s STING DV Platform for design verification of its energy-efficient semiconductor solutions for artificial intelligence (AI) and machine learning (ML) based on the open standard RISC-V instruction set architecture. Esperanto plans to use STING for verifying the […]
Framework enables pre-silicon software development with RISC-V
Antmicro has added support for the Linux-enabled PolarFire SoC revealed earlier by Microchip Technology in the open source Renode software development framework. Microchip PolarFire SoC is a new class of SoC FPGAs that combines the industry’s lowest power mid-range PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V ISA. In a move […]
CPU cores with RISC-V technology now support the custom extension
Andes Technology announced its newly-released AndeStar V5 CPU cores – N25/N25F, NX25/NX25F, A25 and AX25 – support the Andes Custom Extension (ACE) feature. The AndeStar V5 architecture is the result of RISC-V technology incorporated with Andes innovations based on rich experience in serving embedded processor IPs for over 10 years. The ACE feature enables embedded […]
RISC-V SoftCPU contest winners announced
The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), honored the winners of the RISC-V SoftCPU Contest for creating innovative FPGA based CPU implementations targeting the RISC-V ISA. The winners of the contest include: Charles Papon with VexRiscv in […]
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