The Fraunhofer IPMS-developed EMSA5-FS processor core for functional safety based on the open-source RISC-V instruction set architecture is supported by another important debug tool. With the integration into the toolsets of the leading manufacturer of microprocessor development tools Lauterbach, numerous debug functions are now available for the 32-bit RISC-V core. The EMSA5-FS is the first […]
RISC-V
RISC-V embedded development suite speeds RTOS projects
Siemens Digital Industries Software announced today availability of its Nucleus ReadyStart solution for embedded development targeting the fast-growing adoption of the RISC-V architecture. Building on one of the industry’s first commercial real-time operating systems (RTOSes) for RISC-V devices, released in 2021, Siemens’ newest Nucleus ReadyStart embedded development solution includes a host of new features that […]
RISC-V multiprocessor IP cores boast high scalability
MIPS announces its entrance to the RISC-V market, previewing the first products in its eVocore product lineup. The new eVocore P8700 and I8500 multiprocessor IP cores are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard. The new eVocore multiprocessor IP cores are the first MIPS products based on the […]
C++ library available for DevOps toolchains
SEGGER’s emRun++ is a groundbreaking C++ library, fully compatible with the modern 2017 standard. It is used and proven in SEGGER’s multi-platform Embedded Studio IDE for RISC-V and Arm and is now available for licensing to toolchain vendors. emRun++ guarantees fast heap operations with a low instruction count limit, enabling even hard real-time applications to […]
Neuromorphic AI runs on multi-core RISC-V processors
BrainChip Holdings Ltd and SiFive, Inc. have combined their respective technologies to offer chip designers optimized AI/ML compute at the edge. BrainChip’s Akida is a revolutionary advanced neural networking processor architecture that brings AI to the edge in a way that existing technologies are not capable of, with high performance, ultra-low power, and on-chip learning. […]
Software development kit features and real-time C++ support for RISC-V
SEGGER’s Embedded Studio for RISC-V, Version 6, now uses real-time memory management which improves efficiency and response time when allocating and freeing up memory, satisfying requirements for hard real-time in applications written in C++. The new version supports all common RISC-V 32-bit and 64-bit cores, including but not limited to RV64I, RV64E, RV64GC, RV32I, RV32IMA, RV32IMAC, […]
IP core modules facilitate reuse of SoC, MCU, FPGA and ASIC functions
The Fraunhofer Institute for Photonic Microsystems IPMS offers ready-made, platform-independent IP core modules. With IP modules, developers can quickly adopt complete functional areas in standard products such as SoCs, microcontrollers, FPGAs and ASICs. This allows a significant reduction of development times and costs. With EMSA5, Fraunhofer IPMS offers a processor core based on the open […]
Compiler/debugger supports 64-bit RISC-V cores
IAR Systems proudly presented support for 64-bit RISC-V cores in the professional development toolchain IAR Embedded Workbench for RISC-V. With this extended core support, IAR Systems continues to be at the forefront of providing professional development solutions for RISC-V. IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain with everything embedded […]
C/C++ development environment works with RISC-V MCUs
SEGGER announces its partnership with HPMicro Semiconductor Inc. The partnership focuses on making SEGGER’s top-rated, multi-platform IDE Embedded Studio available, free of charge, to all HPMicro’s customers using HPM6000 series RISC-V microcontrollers, boosting the RISC-V ecosystem. Embedded Studio includes all the tools and features expected for streamlined, professional embedded development in C and C++. It comes […]
Test suites for RISC-V now available for high quality security applications
Imperas Software Ltd. announced the beta release of the ImperasDV architectural validation test suites for RISC-V Physical Memory Protection (PMP). The open standard ISA (Instruction Set Architecture) of RISC-V offers developers a wide range of standard extensions and options that support the design of an optimized processor while leveraging the ecosystem of compatibility. The RISC-V Privileged […]
