SEGGER announces a new version of the RISC-V Floating-Point Library with full support for RV32E – the embedded variant of the RISC-V core. The new library leads to a massive reduction in code size for RISC-V applications using floating point. With all arithmetic functions hand-coded in assembly language, the memory footprint of RISC-V applications using […]
Development software incorporates trace and debug for RISC-V processors
IAR Systems has extended the complete development toolchain IAR Embedded Workbench for RISC-V with support for trace as implemented by SiFive Insight, the industry’s first combined pre-integrated trace and debug solution for the freely-available, open-specification RISC-V ISA. In addition to simplifying debugging and helping enforce good coding practices, trace enables extended testing and proof of code coverage, […]
Software supports RISC-V P extension for Packed-SIMD Instructions
IAR Systems announces initial support for the draft RISC-V P extension in its powerful development tools IAR Embedded Workbench for RISC-V. Thanks to this early support for the extension as implemented by Andes Technology, a Premier Founding member of RISC-V International, developers are able to take advantage of a leading development toolchain when starting to […]
Collaboration focuses on development tools for RISC-V-based MCUs
IAR Systems and GigaDevice Semiconductor Inc. announce that they have formed a partnership in order to deliver powerful development tools for GigaDevice’s RISC-V based microcontrollers (MCUs). IAR Systems provides the C/C++ compiler and debugger toolchain IAR Embedded Workbench. The toolchain offers leading code performance for size and speed, as well as extensive debugging functionality with […]
USB-powered debug probe supports trace/debug integrated with RISC-V processor cores
SEGGER’s products are already fully compatible with SiFive’s RISC-V processor cores, and now its J-Link probes deliver support for the new SiFive Insight debug/trace solution. This includes SiFive’s latest Nexus-based trace implementation, which enables ongoing monitoring and recording of processor instruction execution. Via SEGGER’s highly popular J-Link PLUS, PRO and ULTRA debug probe options, plus […]
Software tools support RISC-V processor SoC development tasks
Segger has announced its full support for Nuclei RISC-V processor SoCs. Nuclei System Technology is a leading vendor of RISC-V processor IP in China. In August of 2019, Nuclei and GigaDevice announced the first RISC-V general-purpose MCU, the Bumblebee. Support includes SEGGER’s Embedded Studio IDE, its market-leading J-Link debug probe, and its Ozone debugger. Also […]
RISC-V reference models support processor verification
Imperas Software Ltd., announced the latest enhancements to its range of RISC-V reference models and solutions to support processor verification, with the leading commercial SystemVerilog hardware design verification environments provided by Cadence, Mentor, Synopsys, and also the Metrics cloud-based tools. Working together with lead customers, industry groups and associations, and the Google Instruction Stream Generator […]
Early Access Program for FPGAs enables design of power-efficient applications
The trend towards compute-intensive gateways and edge devices is driving the integration of traditional deterministic control applications with additional embedded processing capabilities needed for smart and secure connected systems. In response, Microchip Technology Inc. is opening the Early Access Program (EAP) for the PolarFire field programmable gate array (FPGA) system-on-chip (SoC). The platform offers the world’s […]
Platform helps implement security features in SoCs
SiFive Inc. announced the release of SiFive Shield, a class-leading new platform security architecture. SiFive Shield is an innovative new approach to SoC design, offering a whole SoC approach to security that enables secure lifecycle management, reduces trusted computing base, and offers a clear root-of-trust. Modern SoC designs require scalable security architectures with greater isolation […]
Real-time system verification tool now available for RISC-V embedded systems
Segger’s SystemView reveals the true runtime behavior of an application by utilizing its real-time recording and visualization capabilities. It uses J-Link and Segger’s Real-Time Transfer (RTT) technology for continuous real-time recording and live analysis. The numerous benefits of SystemView can now be applied to any RISC-V embedded system via System Bus Access (SBA). Freely available […]
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