Synopsys, Inc. announced the availability of the industry’s first Verification IP (VIP) for Compute Express Link (CXL) 2.0 designed for breakthrough performance in data-intensive system-on-chips (SoCs). CXL is the next-generation open standard interconnect that enables an ecosystem for high-speed communication between the CPU and workload accelerators, such as GPUs, FPGAs, and other purpose-built accelerator solutions, as well as memory expansion devices. The technology is built upon the well-established PCI Express infrastructure, leveraging the PCI Express 5.0 physical and electrical interface.
Synopsys VIP for CXL uses next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments and speeds up simulation performance allowing users to run a greater number of tests and accelerate time to the first test. VIP for CXL is natively integrated with Synopsys Verdi Protocol and Performance Analyzer and includes built-in coverage and verification plans for faster verification closure. In addition, Synopsys’ silicon-proven DesignWare CXL IP delivers an x16 link for maximum bandwidth with low latency, supporting all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements.
The CXL 2.0 protocol comes with an increased fan-out, pooling feature set for both physical layer and application layers. New features supported by CXL 2.0 are CXL switching and support for multiple logical devices (MLD); IDE (security) for both CXL.io & CXL.cache/mem; Ability to negotiate CXL 2.0 devices during APN phase and hotplug, CXL enumeration to view CXL device as PCI Express endpoint; Updates for system-level manageability through QoS telemetry, function level reset, global persistent flush, memory interleaving, and compliance test assertions