Synopsys today introduced the industry’s first complete DesignWare USB4 IP solution consisting of controllers, routers, PHYs, and verification IP. The DesignWare USB4 IP operates at up to 40 Gbps, which is twice the maximum data rate of USB 3.2 and is backward compatible with USB 3.x and USB 2.0 systems. The DesignWare USB4 IP supports […]
Tape-outs for SoCs aid early adopters of Arm mobile processor IP
Synopsys announced that Synopsys and Arm have collaborated to enable tapeouts of optimized system-on-chips (SoCs) for early adopters of Arm’s latest mobile processor IP, including Arm Cortex-A78 and Cortex-X1 CPUs, and Mali-G78 GPU. A range of Synopsys solutions, including the Synopsys Fusion Design Platform, Verification Continuum Platform, and DesignWare Interface IP, were used in the design of […]
Design software accelerates development of SoCs for high-end cloud computing, AI apps
Synposys announced the industry’s broadest portfolio of high-quality IP on TSMC’s 5nm process technology for high-performance computing system-on chips (SoCs). The DesignWare IP portfolio on the TSMC process, encompassing interface IP for the most widely used high-speed protocols and foundation IP, accelerates development of SoCs for high-end cloud computing, AI accelerators, networking and storage applications. The combination […]
Chip-design compiler keys on 2.5, 3D multi-die system-in-a-package developments
Synopsys introduced its 3DIC Compiler platform to transform the design and integration of complex 2.5 and 3D multi-die system in a package. It provides an unprecedented fully integrated, high-performance, and easy-to-use environment, offering architectural exploration, design, implementation, and signoff with signal, power, and thermal integrity optimizations, all in one solution. With 3DIC Compiler, IC design […]
High-performance 64-bit ARC processor IP boosts performance by 3X
Synopsys announced the new DesignWare ARC HS5x and HS6x processor IP families for high-performance embedded applications. The 32-bit ARC HS5x and 64-bit HS6x processors, available in single-core and multicore versions, are implementations of a new superscalar ARCv3 Instruction Set Architecture (ISA) and deliver up to 8750 DMIPS per core in 16-nm process technologies under typical conditions, making them […]
Chip design software promotes high-throughput camera and display SoC development
Synopsys announced it is expanding its MIPI camera and display IP portfolio with the DesignWare MIPI C-PHY/D-PHY IP for a range of FinFET processes. The silicon-proven C-PHY/D-PHY IP is compliant with the MIPI C-PHY v1.2 and D-PHY v2.1 specifications for a low-risk solution targeting high-resolution imaging and display SoCs. In addition, the C-PHY/D-PHY meets the stringent functional […]
Ethernet 800G Verification IP targets next-generation networking systems
Synopsys, Inc. announced the availability of the industry’s first verification IP (VIP) and Universal Verification Methodology (UVM) source code test suite for Ethernet 800G. As the requirements for increased bandwidth to support video-on-demand, social networking and cloud services continues to rise, Synopsys VC VIP for Ethernet 800G, based on the Ethernet Technology Consortium (ETC) specification, enables […]
Physically aware RTL design system halves SoC implementation cycle
Synopsys announced the immediate availability of RTL Architect, an innovative product that signifies a shift-left for RTL design closure. Synopsys RTL Architect is the industry’s first physically aware RTL design system, which reduces the SoC implementation cycle in half and delivers superior quality-of-results (QoR). RTL teams are increasingly faced with the challenges of rapidly exploring […]
Security testing software development tool analyzes open source, proprietary code
Synopsys, Inc. announced that on Feb. 18 it will release a major update to the Polaris Software Integrity Platform to extend its static application security testing (SAST) and software composition analysis (SCA) capabilities to the developer’s desktop through the native integration of the Code Sight IDE plugin. These capabilities, the first of their kind, will enable […]
Software development platform reduces noise, reduces memory footprint in SoC designs
Synopsys announced general availability of the VC SpyGlass RTL Static Signoff platform, part of the Synopsys Verification Continuum platform, which builds on the proven SpyGlass technology. The VC SpyGlass platform with multi-core support increases performance by 3X with half the memory footprint. The next-generation platform is enhanced with machine learning technology to reduce noise by […]
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