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SOC design software features verification planning, memory-aware debug and performance analysis

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Synopsys, Inc. announced the availability of the industry’s first Verification IP (VIP) for Compute Express Link (CXL) 2.0 designed for breakthrough performance in data-intensive system-on-chips (SoCs). CXL is the next-generation open standard interconnect that enables an ecosystem for high-speed communication between the CPU and workload accelerators, such as GPUs, FPGAs, and other purpose-built accelerator solutions, as well as memory expansion devices. The technology is built upon the well-established PCI Express infrastructure, leveraging the PCI Express 5.0 physical and electrical interface.

Synopsys VIP for CXL uses next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments and speeds up simulation performance allowing users to run a greater number of tests and accelerate time to the first test. VIP for CXL is natively integrated with Synopsys Verdi Protocol and Performance Analyzer and includes built-in coverage and verification plans for faster verification closure. In addition, Synopsys’ silicon-proven DesignWare CXL IP delivers an x16 link for maximum bandwidth with low latency, supporting all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements.

The CXL 2.0 protocol comes with an increased fan-out, pooling feature set for both physical layer and application layers. New features supported by CXL 2.0 are CXL switching and support for multiple logical devices (MLD); IDE (security) for both CXL.io & CXL.cache/mem; Ability to negotiate CXL 2.0 devices during APN phase and hotplug, CXL enumeration to view CXL device as PCI Express endpoint; Updates for system-level manageability through QoS telemetry, function level reset, global persistent flush, memory interleaving, and compliance test assertions

Synopsys VC VIP for CXL 2.0/1.1 is available today. DesignWare CXL IP Solution is also available now. For more information, visit VC Verification IP for CXL and DesignWare CXL IP

Chip design software works with 3-nm gate-all-around process technology

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Synopsys, Inc. announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform. It has been optimized to provide maximum designer productivity for designers of advanced 5G, HPC, AI, and IoT applications using the Samsung 3nm GAA process technology.

Complexity at advanced nodes means designers are looking for new methods to shorten design cycles. Through close collaboration, Samsung and Synopsys provide a flow that is optimized to overcome design complexity and provide the best possible products for 3nm GAA design. Key features of the flow include in-design electromigration analysis, which shortens design closure time by providing accurate electromigration analysis before the layout is complete. It also includes Live design rule checking (DRC) with Synopsys’ IC Validator physical verification solution, enabling layout engineers to quickly check for design rule violations directly from the layout canvas as they work.

The AMS reference flow provides a proven methodology for designing at 3nm GAA process technology. This methodology, which has been validated by Samsung, includes a full set of documented flows and design examples. Covered topics include design entry, circuit simulation, Monte Carlo analysis, noise analysis, RF analysis, aging, and EM/IR analysis, parasitic simulation, layout, and signoff.

The Synopsys Custom Design Platform is based on the Custom Compiler design and layout environment and includes HSPICE circuit simulator, FineSim circuit simulator, CustomSim FastSPICE circuit simulator, Custom WaveView waveform display, StarRC parasitic extraction, and IC Validator physical verification. The platform features natively integrated StarRC extraction to provide early feedback on the impact of parasitics on circuit behavior, performance, and pioneering visually-assisted layout automation capabilities that simplify the creation of advanced-node layout.

Automotive reference flow streamlines SoC design for ISO 26262 compliance

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Synopsys, Inc. and Samsung Foundry announced the release of a validated automotive reference flow to streamline SoC hardware design for in-system test, implementation, verification, timing, and physical signoff for ISO 26262 compliance. This reference flow is targeted for automotive safety integrity level (ASIL) D autonomous driving and advanced driver-assistance systems (ADAS) applications. In close collaboration with Samsung, the optimized Synopsys automotive reference flow provides SoC architects, designers, and verification engineers with complete differentiated design and IP solutions that deliver complex functional safety (FuSa) analysis, implementation, and verification capabilities. The automotive reference flow utilizes Synopsys’ comprehensive automotive design flow and ASIL D-compliant functional safety processor IP.

ISO 26262 compliance complicates predictable execution of the automotive SoC project, by necessitating manual time-consuming flows which lack scalability, incur significant work overhead, and consume limited machine resources. These challenges drive project managers and designers to adopt new methodologies to reduce resource requirements, minimize manual tasks, and improve the quality of results (QoR). Through close collaboration, Samsung Foundry and Synopsys delivered a comprehensive automotive reference flow optimized to provide the best possible productivity and QoR.

Synopsys’ comprehensive automotive design flow includes unified functional safety verification and native automotive solutions, enabling designers to prove at the planning and implementation phases that their chip safety architecture can achieve target ASILs. Designers can perform FMEA and FMEDA with best-in-class technologies for unified fault campaign management. As part of the shift-left approach introduced by Synopsys, early functional safety analysis at RTL or gate-level can quickly identify candidates for triple-mode redundancy (TMR) and dual-core lock-step (DCLS) redundancy and estimate metrics for target ASIL. Synopsys offers the industry’s first self-test solution instantiated directly into the RTL that tolerates indeterminate digital states while rapidly achieving high fault coverage. Synopsys’ native automotive solutions based on FuSa intent provide the industry’s most comprehensive feature set to implement FuSa mechanisms, such as TMR, DCLS, and Finite State Machine (FSM), perform formal verification, and check and report that safety mechanisms are properly implemented. Comprehensive digital/analog fault injection and simulation can be performed to produce reliable metrics for FMEDA and roll-up. Synopsys solutions are independently ISO 26262 certified to accelerate the deployment and qualification process for ASIL D designs.

The Synopsys functional safety processor integrates hardware safety features, such as redundant processors, error-correcting code (ECC), parity protection, safety monitors, and user-programmable windowed watchdog timers, to detect system errors. Comprehensive documentation related to safety, including enhanced-safety manuals, FMEDA, and design failure modes and effects analysis (DFMEA) reports accelerating SoC-level functional safety assessments. The processor is supported by Synopsys’ ASIL D-compliant toolkit, helping software developers accelerate the development of ISO 26262-compliant codes. In addition, Synopsys offers a broad portfolio of an automotive-grade interface, processor, and foundation IP that can help designers achieve high levels of functional safety, security, and reliability.

Functional safety processor meets requirements for ISO 26262 ASIL D compliance

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Synopsys, Inc. today announced that the DesignWare ARC EM22FS Functional Safety Processor has achieved certification for full ISO 26262 automotive safety integrity level (ASIL) D compliance, meeting both random hardware fault detection and systematic functional safety development flow requirements. The full compliance allows companies to accelerate the development and assessment of their automotive safety-critical SoCs for random and systematic compliance per the ISO 26262 standard.

To meet stringent safety requirements, the ARC Functional Safety Processor offers integrated safety-critical hardware features including error-correcting code (ECC) for memories and interfaces, transient fault protection for internal registers, diagnostic error injection, and an integrated self-checking safety monitor.

The ASIL D compliant ARC EM22FS is a dual-core lockstep processor IP based on the ultra-compact ARC EM Processor family. The IP includes comprehensive safety documents such as failure modes, effects and diagnostic analysis (FMEDA), Safety Manual, Safety Case Report, ISO 26262 Functional Safety Assessment Report, and other safety-related documents to accelerate the functional safety analysis and certification of automotive SoCs. The ARC Functional Safety Processor IP is developed based on the ISO 9001 certified Quality Management System (QMS) for Synopsys DesignWare IP supporting additional automotive quality requirements. The ASIL D compliant DesignWare ARC MetaWare Development Toolkit for Safety, helps software developers accelerate the development of ISO 26262 compliant code. The ARC Functional Safety Processors combined with Synopsys’ essential interface and foundation IP solutions in Synopsys’ automotive ADAS reference design, helps jump-start development of SoC designs for safety-critical applications.

The DesignWare ARC EM22FS Functional Safety Processor and ARC MetaWare Toolkit for Safety are available now.

Silicon design kit optimized for high-bandwidth memory/PCIe/ethernet connectivity

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Synopsys, Inc. announced its collaboration with GLOBALFOUNDRIES to develop a broad portfolio of DesignWare IP for GF’s 12LP+ FinFET solution, including USB4/3.2/DPTX/3.0/2.0, PCIe 5.0/4.0/2.1, die-to-die HBI and 112G USR/XSR, 112G Ethernet, DDR5/4, LPDDR5/4/4X, MIPI M-PHY, Analog-to-Digital Converter, and one-time programmable (OTP) non-volatile memory (NVM) IP. The DesignWare IP is optimized to meet the high-bandwidth memory throughput and reliable, high-performance connectivity demands of cloud computing and AI chips implemented on GF’s 12LP+ solution. This recent collaboration marks another significant milestone of the continuous, successful collaboration between the two companies.

GF’s most advanced FinFET solution, 12LP+ builds upon GF’s established 14nm/12LP platform, of which GF has shipped more than one million wafers. Driving the enhanced performance of 12LP+ are features including a 20-percent SoC-level logic performance boost over 12LP, and a 10-percent improvement in logic area scaling.

Availability

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development, and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys’ extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

Unified electronic/photonic design platform speeds photonic IC design tasks

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OptoCompilerSynopsys, Inc. introduced its OptoCompiler solution for photonic integrated circuit (PIC) design, layout implementation and verification. OptoCompiler is the industry’s first unified electronic and photonic design platform, combining mature and dedicated photonic technology with Synopsys’ industry-proven electronic design tools and methods to enable engineers to produce and verify complex PIC designs quickly and accurately. By providing schematic-driven layout and advanced photonic layout synthesis in a single platform, OptoCompiler bridges the gap between photonic experts and IC designers to make photonic design accessible, fast, and flexible.

Photonic technologies are enabling innovations in data communications, sensing, and imaging. As demand increases for lightning-fast, energy-efficient communications, integrated photonics provides a key enabling element of the solution. However, widespread implementation of PICs has, until now, been impeded because many design tools were intended for electronics rather than photonics. As a result, photonic design has largely been the domain of experts who could build their own tools or repurpose a disparate toolset.

OptoCompiler combines unique capabilities for photonic design with industry-proven EDA capabilities, including:

  • Support for electronic-photonic co-design to ensure scalable design processes
  • Comprehensive features for hierarchical design to enable multiple designers to work closely together to shorten product development cycle times
  • Ability to use dedicated native photonic simulators – in conjunction with industry-standard electrical simulators – for accurate simulation results that account for statistical variations
  • Seamless design and simulation of custom photonic components for inclusion in design alongside process design kit (PDK) components
  • Ease-of-use features such as native optical port and net support, assisted waveguide routing, auto-alignment of photonic circuits, and curvilinear layout synthesis
  • Enabling industry standards: Python, TcL and OptoDesigner for scripting and iPDK technology to support PDK development

Low-power GNSS IP speeds IoT modem development

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Synopsys and Nestwave today announced a collaboration to combine Nestwave’s softcore GPS navigation IP with the Synopsys DesignWare ARC IoT Communications IP Subsystem for a complete low-power global navigation satellite systems (GNSS) solution for integration into IoT modems. The collaboration will provide designers with a power-efficient, high-accuracy GPS solution for battery-operated devices without the additional cost of a dedicated GNSS chip. The joint solution will be presented at the Synopsys ARC Processor Virtual Summit on Wednesday, September 9, 2020.

The ARC IoT Communications IP Subsystem is an integrated hardware and software solution that combines Synopsys’ DSP-enhanced ARC EM9D processor, hardware accelerators, dedicated peripherals, and RF interface to deliver efficient DSP performance for ultra-low bandwidth IoT applications. Nestwave’s GNSS solution takes advantage of the ARC EM9D processor’s efficient DSP capabilities and ability to add dedicated hardware accelerators or custom instructions using APEX technology to reduce frequency requirements, giving customers additional performance bandwidth. The ARC EM9D processor is supported by the MetaWare Toolkit, which includes a rich library of DSP functions, allowing software engineers to rapidly implement algorithms from standard DSP building blocks.

Nestwave has developed an ultra-low power, advanced global navigation satellite systems (GNSS) solution for use in IoT applications. When integrated with an IoT modem such as NB-IoT, Cat M1, LoRa or Sigfox, the solution offers low-cost geolocation for emerging applications such as asset tracking, smart factories, and smart cities, without the need for an external GNSS chip.

Multi-die IC design software keys on Chip-on-Wafer-on-Substrate efforts

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Synopsys 3DIC CompilerSynopsys and TSMC have collaborated to deliver certified design flows for advanced packaging solutions using the Synopsys 3DIC Compiler product for both silicon interposer based Chip-on-Wafer-on-Substrate (CoWoS-S) and high-density wafer-level RDL-based Integrated Fan-Out (InFO-R) designs. 3DIC Compiler provides packaging design solutions required by today’s complex multi-die systems for applications like high-performance computing (HPC), automotive and mobile.

The Synopsys 3DIC Compiler solution provides a unified chip-package co-design and analysis environment for creating an optimal 2.5D/3D multi-die system in a package. The solution includes features such as TSMC design macro support and auto-routing of high-density interposer based interconnects using CoWoS technology. For RDL-based InFO designs, schedules are reduced from months to a few weeks through automated DRC-aware, all-angle multilayer signal and power/ground routing, power/ground plane creation, and dummy metal insertion, along with the support for TSMC design macros.

For CoWoS-S and InFO-R designs, dies need to be analyzed in the context of the package and the overall system.  Die-aware package and package-aware die power integrity, signal integrity, and thermal analysis are critical for design validation and signoff. Integration of Ansys’ RedHawk family of chip-package co-analysis solutions in 3DIC Compiler meets this critical need, enabling seamless analysis and faster convergence to an optimal solution. Customers can achieve smaller designs and higher performance by eliminating overdesign.

USB4 IP covers controllers, routers, PHYs

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DesignWare USB4 IPSynopsys today introduced the industry’s first complete DesignWare USB4 IP solution consisting of controllers, routers, PHYs, and verification IP. The DesignWare USB4 IP operates at up to 40 Gbps, which is twice the maximum data rate of USB 3.2 and is backward compatible with USB 3.x and USB 2.0 systems. The DesignWare USB4 IP supports multiple high-speed interface protocols, including USB4, DisplayPort 1.4a TX, PCI Express, and Thunderbolt 3 for efficient data transfer and simultaneous delivery of data, power, and high-resolution video through a single USB Type-C cable.

Synopsys has already achieved successful test chip tapeout of its USB4 IP in an advanced 5nm FinFET process, demonstrating the robustness of the IP across process, voltage, and temperature variations. The new DesignWare USB4 IP is designed to meet the functionality, power, performance, and area requirements of a broad range of storage, PC, and tablet SoC designs, as well as software development, debug and easy deployment of artificial intelligence (AI) applications at the edge. As the leading provider of USB IP for nearly two decades, Synopsys is enabling designers to lower the risk and adoption barrier of integrating USB4 functionality into their SoCs.

The DesignWare USB4 Router IP enables efficient connectivity between all supported protocols and are pre-verified with the USB4 Controller IP for millions of simulated CPU hours to help ensure long-term performance and interoperability. The DesignWare USB4 PHY IP offers a highly efficient power profile while supporting all required protocols in approximately one-third the area of independent PHYs. The Synopsys USB4 Verification IP Solution includes built-in coverage, protocol checkers, Verdi protocol-aware debug technology for Host and Device router topologies, and a comprehensive source code test suite for USB, PCI Express, and DisplayPort tunneled protocols to accelerate verification closure.

DesignWare USB4 PHYs, device router, controllers, and Synopsys Verification IP are available for lead customers now.

Tape-outs for SoCs aid early adopters of Arm mobile processor IP

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Tape-outs for SoCsSynopsys announced that Synopsys and Arm have collaborated to enable tapeouts of optimized system-on-chips (SoCs) for early adopters of Arm’s latest mobile processor IP, including Arm Cortex-A78 and Cortex-X1 CPUs, and Mali-G78 GPU. A range of Synopsys solutions, including the Synopsys Fusion Design Platform, Verification Continuum Platform, and DesignWare Interface IP, were used in the design of smartphones, laptops, other mobile devices, 5G, augmented reality, and machine learning products based on Arm’s new processors. To help designers accelerate time-to-market (TTM) and achieve optimal power, performance, and area (PPA) targets, Synopsys QuickStart Implementation Kits (QIKs) are available today.

Leveraging the collaboration that enabled successful early adopter tapeouts, the QIKs provide implementation scripts and reference guides and take advantage of Synopsys Fusion Compiler technology to deliver enhanced PPA and faster turnaround. To help designers achieve their targets quickly and confidently, Synopsys offers design services based on extensive experience hardening Arm processors. The services available range from QuickStart implementation through turnkey core hardening.

The Synopsys Fusion Design Platform has been leveraged for optimized implementation of the new mobile cores and incorporates many Synopsys industry-leading products, including:

  • Fusion Compiler design, Design Compiler NXT synthesis, and IC Compiler II place-and-route system for efficient, low-power design implementation
  • Signoff closure with PrimeTime PBA-based ECO with power recovery and exhaustive PBA along with StarRC simultaneous multi-corner extraction
  • Early, accelerated design optimization for power integrity and reliability with the RedHawk Analysis Fusion signoff-driven flow within Fusion Compiler and IC Compiler II place and route

Early adopters of Arm’s new premium mobile platform are using Synopsys Verification Continuum solutions extensively with:

  • Earlier, faster, scalable software development and test from anywhere at any time with Synopsys Virtualizer Development Kit (VDK) with Arm Fast Models for Cortex-A78 and Cortex-X1 CPUs
  • Synopsys VCS® simulation with fine-grained parallelism technology for Arm Cortex-A processors
  • Synopsys industry-leading verification IP and test suites for the latest Arm AMBA® interconnect
  • Synopsys ZeBu Server for system verification and benchmarking
  • Synopsys HAPS hardware for high performance, scalable FPGA-based prototyping proven with latest Arm cores

Synopsys’ high-quality DesignWare Interface IP enables rapid development of mobile Arm-based SoCs. DesignWare IP for mobile markets includes controllers and PHYs for USB, DDR/LPDDR, PCI Express, MIPI, HDMI, Bluetooth and mobile storage interfaces, and is shipping in billions of units today.

QIKs for key Arm processors are available today at https://www.synopsys.com/arm-opto. More information about Synopsys’ solutions for designing Arm-based products is available at: https://synopsys.com/Arm.