Synopsys, Inc. announced the availability of its new DesignWare tRoot(TM) Hardware Secure Module (HSM) and ARC SEM130FS Safety and Security Processor IP solutions with integrated functional safety features to accelerate ISO 26262 certification of automotive systems-on-chips (SoCs). The ASIL B compliant tRoot HSM for Automotive adds hardware safety mechanisms for protection against permanent, transient, and latent […]
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Chip IP for PCI Express 6.0 includes controller, PHY and verification IP
Synopsys, Inc. announced the industry’s first complete IP solution for the PCI Express (PCIe) 6.0 technology that includes controller, PHY, and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys’ widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features […]
SoC power-aware emulation verifies power workloads for multi-billion gate designs
Synopsys, Inc. announced the immediate availability of ZeBu Empower emulation system, delivering breakthrough technology for fast hardware-software power verification of multi-billion gate SoC designs. The performance of ZeBu Empower enables multiple iterations per day with actionable power profiling in the context of the full design and its software workload. With ZeBu Empower, software and hardware designers can utilize the […]
Security modules help thwart attacks in HPC SoCs using PCIe 5.0/CXL 2.0 interfaces
Synopsys, Inc. announced the availability of the DesignWare Integrity and Data Encryption (IDE) Security Modules to help designers protect against data tampering and physical attacks in high-performance computing (HPC) SoCs using the PCI Express (PCIe) 5.0 architecture or Compute Express Link (CXL) 2.0 interface. The DesignWare IDE Security Modules protect sensitive data with efficient encryption, decryption, […]
SOC design software features verification planning, memory-aware debug and performance analysis
Synopsys, Inc. announced the availability of the industry’s first Verification IP (VIP) for Compute Express Link (CXL) 2.0 designed for breakthrough performance in data-intensive system-on-chips (SoCs). CXL is the next-generation open standard interconnect that enables an ecosystem for high-speed communication between the CPU and workload accelerators, such as GPUs, FPGAs, and other purpose-built accelerator solutions, as well […]
Chip design software works with 3-nm gate-all-around process technology
Synopsys, Inc. announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform. It has been optimized to provide maximum designer productivity for designers of advanced 5G, HPC, AI, and IoT applications using the Samsung 3nm […]
Automotive reference flow streamlines SoC design for ISO 26262 compliance
Synopsys, Inc. and Samsung Foundry announced the release of a validated automotive reference flow to streamline SoC hardware design for in-system test, implementation, verification, timing, and physical signoff for ISO 26262 compliance. This reference flow is targeted for automotive safety integrity level (ASIL) D autonomous driving and advanced driver-assistance systems (ADAS) applications. In close collaboration with […]
Functional safety processor meets requirements for ISO 26262 ASIL D compliance
Synopsys, Inc. today announced that the DesignWare ARC EM22FS Functional Safety Processor has achieved certification for full ISO 26262 automotive safety integrity level (ASIL) D compliance, meeting both random hardware fault detection and systematic functional safety development flow requirements. The full compliance allows companies to accelerate the development and assessment of their automotive safety-critical SoCs for random […]
Silicon design kit optimized for high-bandwidth memory/PCIe/ethernet connectivity
Synopsys, Inc. announced its collaboration with GLOBALFOUNDRIES to develop a broad portfolio of DesignWare IP for GF’s 12LP+ FinFET solution, including USB4/3.2/DPTX/3.0/2.0, PCIe 5.0/4.0/2.1, die-to-die HBI and 112G USR/XSR, 112G Ethernet, DDR5/4, LPDDR5/4/4X, MIPI M-PHY, Analog-to-Digital Converter, and one-time programmable (OTP) non-volatile memory (NVM) IP. The DesignWare IP is optimized to meet the high-bandwidth memory throughput […]
Unified electronic/photonic design platform speeds photonic IC design tasks
Synopsys, Inc. introduced its OptoCompiler solution for photonic integrated circuit (PIC) design, layout implementation and verification. OptoCompiler is the industry’s first unified electronic and photonic design platform, combining mature and dedicated photonic technology with Synopsys’ industry-proven electronic design tools and methods to enable engineers to produce and verify complex PIC designs quickly and accurately. By providing schematic-driven […]
