Synopsys announced its new native automotive solutions for more efficient system-on-chip (SoC) design. The accelerating evolution of vehicle technologies means that more automotive chips are required to satisfy higher automotive safety integrity levels (ASILs) for autonomous driving and advanced driver-assistance systems (ADAS). Synopsys’ native automotive design solutions enable designers to achieve their target ASILs by […]
Software platform speeds development of next-gen ARM processor SoCs
Synopsys announced that Synopsys, Arm, and Samsung have actively collaborated on solutions to enable early adoption of the next-generation Arm-based processor. Design-ready solutions are based on the artificial intelligence (AI)-enhanced, cloud-ready Fusion Design Platform from Synopsys, along with Arm Artisan Physical IP and POP IP for Samsung Foundry’s advanced 5LPE process. These solutions will accelerate […]
Functional safety verification software speeds time-to-certification for IPs, SoCs
Synopsys announced the industry’s first and most comprehensive unified functional safety verification solution to accelerate time to ISO 26262 certification for automotive IP and semiconductor companies targeting the highest Automotive Safety Integrity Levels (ASIL D). As part of the solution, Synopsys introduced VC Functional Safety Manager, a FMEA/FMEDA and fault classification automation technology enabling architects, […]
Unified software platform tailors hardware architecture to algorithmic code
Xilinx, Inc. announced Vitis (pronounced Vī-tis), a unified software platform that enables a broad new range of developers – including software engineers and AI scientists – to take advantage of the power of hardware adaptability. The Vitis unified software platform automatically tailors the Xilinx hardware architecture to the software or algorithmic code without the need for hardware […]
Digital SoC design software brings zero iterations between implementation and signoff
Synopsys announced the Synopsys PrimeECO design closure solution, the industry’s first signoff-driven solution that achieves signoff closure with zero iterations. Signoff closure has emerged as one of the top challenges in digital design implementation, consuming up to 50 percent of the design schedule, mainly driven by rapidly increasing signoff scenarios and physical complexity at advanced […]
Ethernet PHY IP handles 800G networking apps
Synopsys announced its DesignWare 112G Ethernet PHY IP on TSMC’s N7 process supporting true long-reach channels for up to 800G networking applications. The DesignWare 112G PHY, based on Synopsys’ silicon-proven 56G Ethernet PHY available in multiple FinFET processes, delivers PAM-4 signaling for more than 35dB channel loss across optical, copper cables, and backplane interconnects. The […]
Processor IP supports ASIL B and ASIL D safety levels to simplify safety-critical automotive SoC development
Synopsys announced new functional safety (FS) derivatives of its popular DesignWare ARC processor IP to simplify and accelerate the development of automotive system-on-chips (SoCs). The safety-enhanced processor portfolio, which includes the Synopsys DesignWare ARC EM22FS, HS4xFS, and EV7xFS processors, covers a broad range of automotive use cases from ultra-low power control modules to artificial intelligence […]
Chip design IP enables low-latency data comm among SoCs, general-purpose accelerators, memory expanders, smart I/O devices
Synopsys announced the availability of its complete DesignWare Compute Express Link (CXL) IP solution consisting of controller, PHY, and verification IP for AI, memory expansion, and high-end cloud computing system-on-chips (SoCs). The CXL protocol enables low-latency data communication between the SoC and general-purpose accelerators, memory expanders, and smart I/O devices requiring high-performance, heterogenous computing for […]
IC place-and-route software cuts power and chip area, speeds timing in new designs
Synopsys announced immediate availability of the latest release of its flagship IC Compiler II place-and-route system that includes several new innovative technologies to deliver superior quality-of-results (QoR) and fastest time-to-results (TTR) for the next wave of leading-edge designs across a wide range of vertical markets, including automotive, cloud computing, AI, networking and wireless applications. Continued […]
IC place-and-route package optimizes power use of chip designs
Synopsys announced immediate availability of the latest release of its flagship IC Compiler II place-and-route system that includes several new innovative technologies to deliver superior quality-of-results (QoR) and fastest time-to-results (TTR) for the next wave of leading-edge designs across a wide range of vertical markets, including automotive, cloud computing, AI, networking and wireless applications. Continued […]
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