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Emerging memory technologies – Virtual Roundtable (part 1 of 2)

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Hosted by Jeff Shepard

In this Virtual Roundtable session on emerging memory technologies, we are joined by Nando Basile (NB), Technology Marketing Manager for Memory with X-FAB; Bob Brennan (BB), Vice President of Emerging Memory at Micron; and Mark Reiten (MR), Vice President, Licensing Business Unit, Silicon Storage Technology (SST), a wholly-owned subsidiary of Microchip Technology.

JS: What are the important design considerations when using emerging memory technologies such as MRAM, ReRAM, etc. in applications?

Nando Basile (NB), Technology Marketing Manager for Memory with X-FAB

NB: At X-Fab, we deal with memory specifically from an embedded perspective, rather than producing standalone memory devices. As everything is done at the die level, it must be compatible with all the other functionality that will be present in the device. We have already had a great deal of success with the implementation of SONOS into automotive ICs, shipping large unit quantities. For emerging memory technologies (like ReRAM), we are currently looking at ways to integrate this onto customers’ devices, for applications like edge computing and medical.

BB: For applications, there is a classic performance vs. capacity triangle for memory and storage technologies. At the top of the triangle is DRAM, which is optimal for latency and endurance for the most demanding volatile applications. At the base of the triangle are flash technologies (TLC, QLC), which are optimal for block storage applications. With a combination of innovative designs and massive capital investment, DRAM and NAND will continue in their roles at the top and bottom of the hierarchy for the next decade.

Bob Brennan (BB), Vice President of Emerging Memory at Micron

MRAM, such as STTRAM, has the advantage of easier integration with logic semiconductor processes. However, STTRAM has slightly higher latency and energy than DRAM with less endurance and has design implementation challenges in achieving density. As such, the industry adoption of logic + STTRAM remains to be seen. RRAM is an interesting lower latency block storage technology, and it remains to be seen if the economics of the areal density will lead to broad market deployment.

JS: Are MRAM, ReRAM, and other emerging NVM technologies ready for prime time? Are controller breakthroughs the bottleneck to enabling the growth of MRAN, ReRAM, etc.? Or is there another factor holding back growth?

NB: growth? These technologies are already starting to see traction in standalone memories, mostly because of their promising boost in density and low-power performance. In relation to embedded applications, however, they are still not totally mature, mostly in terms of technology integration and design optimization. This means that full scale embedded implementation is some way off yet, except maybe for some initial niche applications. We definitely see a lot of potential for ReRAM in the medium term – due to the low number of additional masks required, as well as with respect to its ultra-low-power performance, improved access time, and execute-in-place capabilities.

BB: There have been many credible research papers published on MRAM, ReRAM, and other technologies in conferences such as ISSCC, and these types of technologies continue to be an active research area for many semiconductor companies. Controller technologies are not holding back the adoption of new memory technologies. The greater the raw bit error rate of a memory technology, the more sophisticated the error needs to be. The lower the endurance, the more sophisticated the ASIC and the firmware need to be at managing the media. Fundamental changes to software take two Olympic cycles (eight years), and this is a major industry investment for the ecosystem to adopt a new layer in the memory and storage hierarchy.

JS: What emerging memory technologies (either volatile or non-volatile) do you expect to have the largest impact in the near-term, and where will they have the greatest use?

Mark Reiten (MR), Vice President, Licensing Business Unit, Silicon Storage Technology (SST), a wholly-owned subsidiary of Microchip Technology

MR: I would like to address all three of the preceding questions at once: MRAM, ReRAM, and other emerging memories have all been emerging for a long time.  These technologies all have disadvantages when compared with the Floating Gate and Charge Trapping technologies that have dominated both standalone and embedded memory products for the last 50 years.

Let’s start with MRAM.  The industry has been developing MRAM for more than 20 years.  The cell technology has evolved from Magnetic Tunnel Junction (MTJ) to Spin Torque Transfer (STT) architectures.  The older MTJ architecture has been in production for the last decade, serving niche markets like NVSRAM replacement (Everspin) in the datacenter.  No high-volume usage exists for these technologies due to product cost and inability to meet required specifications.

The STT architecture is the current approach used at advanced nodes, and it is entering production at the 28/22nm process nodes for embedded use.  Both production and reliability challenges remain and are barriers to broad adoption of MRAM.  The STT materials stack is comprised of 18-20 very thin layers of magnetic and dielectric materials utilizing many (Co, Ru, Mg, Fe, B, Pt) constituent elements.  Depositing these layers requires atomic layer deposition, which is more expensive than other deposition techniques.  Layer thickness control requirements exceed current (and any future known) in line metrology capabilities, so it is very hard to keep the process controlled, and process excursions happen more frequently as a result.  The stacks are built using alternating layers of material, so etching requires a gas change to etch each layer.  Gas changes take minutes per cycle, which limits the throughput to about one wafer per hour.  This means an expensive etcher can only process about 20-25 wafers per day (dramatically lower throughput than other technologies).  Low etch throughput and the complex, time-consuming layer deposition leads to high manufacturing costs.  The stack complexity and layer thickness control (or lack thereof) lead to inconsistency and reliability issues.

MRAM has been qualified at TSMC, Samsung, and GLOBAL FOUNDRIES for production as an embedded technology at 28/22nm nodes and has gained a small following who can tolerate the cost, non-competitive specifications, magnetic field susceptibility, and other reliability constraints of the technology.  This is despite the fact that MRAM is inferior to embedded floating gate technology in read speed, read/write power, and data retention.  There is hope the technology can be improved over time, and the early adopters may feel they will gain some advantage if they are the first to accumulate field data for MRAM.  I remain skeptical and believe these early adopters will struggle mightily and potentially fail in the market.

ReRAM has been in development for more than 15 years.  It is also entering production at 28nm and also at 40nm.  The main advantage of ReRAM is cost.  Many different ReRAM stacks have been researched, including metal oxides (HfxOx, TaxOx, etc.), chalcogenides, and perovskites, but most of the production level work has been focused on the metal oxide materials stacks.  The materials stacks are much simpler than MRAM and thus require less processing to manufacture.  The disadvantage of ReRAM is even worse program/erase (Set/Reset) power, read power, read speed, and significant reliability compared to MRAM.  This means ReRAM is a far cry from the industry-standard Floating Gate memories in terms of supported specifications and reliability.  Regardless, TSMC is making ReRAM available on 40nm (PMIC products) and 22nm (Smart Card products) and does have some adoption for low-density applications in which the memory macro can be burdened by significant redundancy and overhead to overcome the reliability issues.

The other major difference between emerging memories and Floating Gate technologies is where in the process stack, they are implemented.  Floating Gate memories are built in the front end of the process, with the device being built alongside the transistors from the substrate up.  This means more process complexity but also provides significant advantages in speed and reliability.  The emerging memory cells are deposited in Vias somewhere in the metal layers, which means they don’t interfere with the process front end.  This has not been a differentiator so far, but on 16nm and below, where FinFet structures are used to support transistor scaling, there is much debate in the industry about the feasibility of integrating floating gate memories in the process front end.  At SST, we are convinced we can do it and are engaging with major foundry partners now on evaluation of such technologies.

In summary, I believe MRAM and ReRAM will have a place in low-end microcontroller applications that don’t require high performance or high reliability, but they will not push aside Floating Gate memories now or in the future due to their limitations.  I think Scotty from Star Trek said it best, “Captain, you can’t defy the laws of physics.”

BB: Technologies such as 3D XPoint™ cross over into the non-volatile performance domain, which enables a new layer in the memory hierarchy. With up to 1,000 times lower latency and exponentially greater endurance than NAND, it enables high-speed, high-capacity data storage close to the processor. New operating systems have been written to take advantage of this layer (example: PMEM.IO), and new applications are being written to talk directly to this layer (example: DAX). These new OSes and applications will optimize their data placement in DRAM, 3DXP, and NAND to satisfy new use cases.

Micron’s 3D XPoint memory structure (source: Micron)

JS: How large of an impact do you expect to see from 3D memory technologies? At the chip level? At the package level?

NB: Though 3D stacking is already witnessing an uptake in data center, enterprise, and even consumer applications, one major concern from an automotive standpoint is how to deal with issues like thermal management (particularly ways in which to keep thermal drift under control).

BB: At the chip level, the industry has risen to the challenge of scaling flash technology with innovative 3D structures. The 3D structure of 3D XPoint™ has been well-publicized as a means to optimize both density and performance. At Micron, we are strong believers in the power of 3D memory technologies in flash and are continually innovating at the chip level to enable the technology to continue to scale.

Many exciting new 3D package technologies combine logic and memory and bring them closer together than ever before for benefits in both performance and power. One example is mobile platforms, where the tight integration of computation, DRAM, and flash have enabled small Z-heights at low thermal density, which in turn enable the increase of capabilities in an ultra-thin device.

How to create and run reusable register-test models

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by Matthew Ballance, Mentor, a Siemens Business

Register tests are a very useful smoke test at all design levels — from IP to subsystem to SoC. While the built-in register-test sequences in the UVM library are useful at the IP level, capturing register-test intent in a PSS model makes register-test functionality portable from the IP to the SoC level and provides more flexibility in controlling which registers are checked in a given test run.

In the first article of this four-part EEWorld series, we showed you how to capture register models for subsystem or SoC level tests. In this article, we show you how to produce register-access tests and run them.

Generating register-access test intent

First, we need to create a PSS model of the register-access test intent, which must be constrained, based on the registers in the design tested. Fortunately, we already captured all the information needed to generate these constraints in our register model (see Part 1).

Our register-creation tool may be able to construct PSS register tests directly as one of its outputs. If not, then one approach to automating test intent creation is to run some SystemVerilog code that iterates through the UVM register model and writes out the PSS register-test intent. The code below shows a UVM test that calls a class named regmodel2pss to create PSS test intent from the UVM register model.

The result is a portable stimulus description that captures the register-test intent for the subsystem register map. The code below is the first portion of the PSS component and PSS action generated to test the register model.


The action (named from the register-block name) declares three rand fields. The reg_id field contains an ID for the targeted register and ranges between 0 and the number of registers minus 1. The flip_bit field specifies the register bit to be tested. flip_bit and reg_addr are auto-constrained based on the register id to ensure the action produces a valid register address and flip_bit based on the tested register. A PSS coverage model can also be automatically generated to ensure that all registers and all bits within the registers are covered, as shown below.


The test scenario shown below is built on top of the core action that encodes the test intent. Once we have the core register-test intent, we need to integrate it into a top-level PSS scenario. While our core register-test intent was automatically derived from the register model, our top-level register test scenario will be written by hand.


The test scenario is encapsulated in a top-level component, as required by PSS. Because we will use the action from this component, we generate an instance of the register-test component (subsys_reg_block_c) inside the top-level component. In our top-level action (my_subsys_regtest_a), we create an instance of the subsys_reg_block_regs_a action named testbit. Inside this action is an instance of the register-test fields and covergroup. In the top-level action’s activity, we run testbit 100 times, which means that we will test 100 register bits each time our test runs.

Adding the test realization layer

Now we need to connect this test intent to specific verification environments with test realization, as our top-level test scenario doesn’t actually do anything until it includes test realization. Fortunately, PSS allows us to easily layer in test realization without changing the core description — in this case, the subsys_reg_block_regs_a action. The code below is a test realization description for SystemVerilog that leverages the PSS procedural interface. The signature of an external function is declared and that function is invoked from the exec block of an action


In the test realization snippet above, we use a PSS target-template exec block to specify a snippet of assembly code (RISC-V in this case) that must be generated to test a register bit. The curly braces (e.g., {{reg_addr}}) are used to reference the current value of a field in the PSS model and substitute that value into the generated code. Doing test realization in assembly language certainly has its limitations, but PSS makes it possible when that’s the technique that is needed. This style of test realization works for any environment that supports callable procedures; e.g., C, C++, SystemVerilog, etc. In most cases, our bare-metal embedded software tests for our SoC will be written in C. But, what if we needed to produce an assembly-language test? Fortunately, PSS provides a way to do this as well!

Running the PSS tests

Now that we have test intent and test realization to test access to our registers, we can begin running tests. In a UVM environment, PSS gives us the flexibility to either pre-generate directed tests or run a PSS solver engine while running simulations.

The directed UVM test shown below is very easy to understand, and it always does exactly the same thing.


If we are able to use C in our bare-metal software environment, we can use the testbit function implementation and the PSS procedural interface to generate the C test code, as shown below. But what if we want our tests to do something slightly different whenever we run different seeds? This is where running a PSS solver engine with simulation is advantageous. Running the same sequence with different seeds results in different behavior, and PSS tools provide dedicated features for dynamically partitioning tests across simulations running in regression.


However, if we need to use assembly code, we can use our target-template exec block test realization to generate a fully standalone test. A snippet from that test is shown below with tests for two register/bit combinations.

Conclusion

Both the input files to register-generation tools and the resulting UVM register model contain sufficient information to automatically create portable stimulus test intent. This makes it very easy for register-generation tools to add support for portable stimulus tests. It also makes it very easy to derive portable stimulus tests from existing UVM register models, regardless of how they were constructed. Either way, the result is more verification automation with PSS!

Additional Resources:

Making Legacy Portable with the Portable Stimulus Specification

Automating Tests with Portable Stimulus from IP to SoC Level

Matthew Ballance is a Product Engineer and Portable Stimulus Technologist at Mentor Graphics, working with the Questa inFact Portable Stimulus product. Over the past 20 years in the EDA industry, he has worked in product development, marketing, and management roles in the areas of HW/SW co-verification, transaction-level modeling, and IP encapsulation and reuse. Matthew is a graduate of Oregon State University.

 

Considerations for improving 3D NAND performance, reliability, and yield

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by Mark Puttock, Director Advanced Deposition and Plating, office of CTO, Entegris

Even as 3D NAND races toward maturity and becomes a mainstream technology, chipmakers know there is still more to achieve to meet worldwide consumer and business data demands at lower costs, given the extreme complexities involved.

As with previous technologies, focusing on process efficiencies, materials innovations, and contamination control will optimize manufacturing processes, resulting in better performance, increased yield, and reduced costs.

Optimize high-aspect-ratio etching through materials development

Creating complex 3D structures with very high-aspect-ratio (HAR) features is complicated and requires extreme precision and, ultimately, process uniformity and repeatability to achieve scale.

Precision in etching extreme HAR features is critical for optimizing channel holes and trenches for cell access, as well as its unique staircase structure architecture, which connects the cells to the surrounding CMOS circuitry for reading, writing, and erasing data.

One example of an Etch challenge is the hard mask material typically used for HAR etching. It’s typically amorphous carbon, and its job is to protect patterned areas of material while allowing features to be exposed to Plasma Etching based material removal, but it’s reaching the limit as it is not plasma-resistant enough to do this job as aspect ratios increase. Some of the possible solutions to this challenge will require innovative new materials and development measures to bring higher resistance, stability, repeatability, and optimization to critical etch processes.

If the vertical pitch of the memory stack is around 50 nm, then a 96-layer stack of cells is in the order of 4.8 μm high. This corresponds to a challenging aspect ratio of ~100:1. In addition, as the cell stack comprises stacked pairs of silicon nitride (Si3N4) at the cell level and silicon dioxide (SiO2) to isolate cells, it is extremely difficult for dry etch engineers to achieve a continuous and straight profile while maintaining high enough selectivity to the amorphous carbon hard mask to reach the bottom of the structure. This is an area where engineers should look for significant material modifications, or even a new material, to help overcome these challenges.

Additionally, as multilayer stack heights increase, so does the difficulty in achieving consistent etch and deposition profiles at the top and the bottom of the memory array. For example, given a ratio of ~100:1, the selective removal of Si3N4 in the memory stack becomes a wet-etch challenge. The difficulty is removing the Si3N4 consistently at the top and bottom of the stack and across the wafer, without etching any of the SiO2. Below 96 layers, this task is performed using hot phosphoric acid (~160°C); however, at 96 layers and above, a specially formulated wet etch chemistry is needed to improve process margin.

Eliminate the slowdown

As the stack gets taller, the silicon channels extends longer, and the speed of the device becomes limited by the mobility of electrons travelling through the channels. Germanium doping (currently in development) is one known method for improving electron mobility, and suppliers are working to find even more efficient means of providing germanium dopants for 3D NAND.

The requirement is to achieve uniform doping along an HAR silicon channel approximately 50 nm in diameter and several microns deep. A promising approach may be to replace the current practice of supplying germane (GeH4) gas diluted in hydrogen with a process that uses pure germane. The objective is to look for the best option to maximize the conductivity of the channel and preserve the operational speed of the device.

The purpose of the stair structure in 3D NAND is to provide access to cells at the bottom of the NAND stack thereby allowing the deposition of tungsten (W) to form the word-lines that allow access to the cell control gates from the outside peripheral circuitry. There is one step for every layer of cells, and as more cells are stacked, the staircase gets longer. Increasingly long lengths of conductor are needed to run the length of the staircase (top to bottom, on the order of 10 μm), which in turn introduces higher resistance that affects device performance.

To address conductivity issues as the stack increases in height, it may be necessary to apply alternative metals to tungsten, which is the current standard. Chemical elements such as cobalt, ruthenium, or molybdenum have lower resistivity and better reliability at thin dimensions and could become essential to maintaining overall device performance. The challenge is developing high performance precursors that can deposit these metal films in Atomic Layer Deposition mode.

Establish defect controls early in the supply chain

As the number of memory cells increase in a 3D stack, a defect in a single cell could affect the performance of the entire cell string and hence the device. As a result, all potential contamination areas must be identified and proper steps taken to avoid any and all imperfections. Those steps range from raw materials, to synthesis of chemistries, handling of chemistries, and finally dispensing to the wafer.

For example, the presence of particulates in one cell can effectively kill an entire cell string. Also, metallic contamination (e.g. Fe, Cr, etc. from stainless steel) can destroy the cell electrical properties if they find their way to the cell layers. Likewise, large quantities of plasma etch byproducts from billions of HAR channel holes can adsorb into wafer carrier equipment and later evolve causing defects on the wafer structure. Innovations in wafer carriers (FOUPs) are required to counteract this effect. Lastly, photosensitive masking material (Photoresist), which is required at high viscosity to pattern such HAR features, is prone to bubble formation that leads to patterning defects. Innovations in combined pumping, filtration and dispensing are made to avoid such bubble formation.

Every generation of 3D NAND is becoming more sensitive to contamination, as with shrinking geometries in general, so material purity is critical. Without adequate filtration and purification, process requirements that enable increased layers and dimension shrinkage for advanced chip development cannot be achieved.

Closer collaborations between integrated device manufacturers, original equipment manufacturers, and materials makers/contamination experts across the supply chain will allow process innovations that continue to enable 3D NAND into the foreseeable future. With vertical cell stacking architecture clearly moving toward 128, 256, and perhaps beyond, the industry will achieve higher-performing, more reliable devices with greater capacity and lower cost per bit.

 

How to create energy-efficient IIoT sensor nodes

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IIoT sensor nodes

by Noel O’Riordan and Tommy Mullane, S3 Semiconductors

When you’re designing sensor node devices destined for the industrial internet of things (IIoT), chances are they need to be battery-powered. And given the number of these expected to be deployed, and their often-remote locations, changing or charging a battery frequently isn’t an option. Your device, therefore, needs to be exceptionally energy-efficient, which demands you design everything from the overall system to its individual circuits to minimize energy use.

The challenge is that anyone energy-related design decision is likely to have knock-on effects elsewhere. And then there are less obvious things that can play havoc with battery life. For example, while we know the RF transmitter will generally be a big energy user, it can sometimes be the receiver or power consumption during sleep mode that causes the battery to drain fast. We’ll explore this below.

Creating an optimal design

The good news for designers is that by following a number of overarching principles, you’ll be well on the way to creating an energy-optimized product.

Firstly, using a single custom integrated circuit (IC) is cheaper, smaller and more power-efficient than using 2D-IC or 3D-IC multi-chip packaging. This integrated, system-on-chip (SoC) approach cuts down on the number of power-hungry input/output (I/O) drivers that would be needed on a standard, circuit-board-based implementation.

Duty cycles

Next, you need to understand how the duty cycle affects energy use over your device’s lifetime. Every microjoule you draw from the battery matters when you’re aiming for very long lifespans, but then it isn’t feasible to create a device that only ever consumes a few microwatts at a time.

Instead, planning your duty cycle enables your device to do things that require more significant amounts of power for brief periods, and offset these with savings at other times.

Optimizing the RF system

Let’s look in more detail at the RF subsystem, one of the most power-hungry parts of your device. Controlling how much power the transmitter consumes is relatively straightforward: simply shut it down after delivering the required data. But the receiver may remain active, perhaps because of timing uncertainty, to wait for acknowledgments from the device(s) to which it sent the data, or to listen for other incoming messages. Consequently, though the receiver uses less instantaneous power than the transmitter, you may find it uses more over your product’s total lifespan.

To maximize efficiency, you can put as much of your circuitry as possible in a low-activity state, until your RF receiver detects a signal. You can also cut the time your receiver is active – though this will make your device less responsive to commands from outside.

Processor and memory

Elsewhere, it’s essential you address the duty cycle of your processor core and memory subsystem. While many designs rely on the processor to run the software that underpins fundamental activities (collecting sensor data or passing this to the transmitter, for example), this work is typically straightforward, meaning it doesn’t need the processor. Instead, consider using a programmable state machine or custom ICs. These can operate without the processor, and use much less power. Consequently, you don’t need to power your memory either.

Sleep time

When you consider how long IIoT nodes are likely to spend in “sleep” mode, it’s important to look at energy usage during these periods: what may seem like relatively small amounts will add up to something very significant over a device’s lifetime.

Current leakage in subsystems that must continue to operate is a particular issue. Think about using real-time clocks and nanoamp-level interrupt controllers. In certain situations, it can be tempting to disable interrupts for external events, and only run the real-time clock. This isn’t always the best option, however, because it requires your system to wake regularly to check for any inputs that may have occurred. By choosing an interrupt controller with sufficiently low energy requirements, it may be better to keep it running, so you can respond to things as they happen.

Next, what do you do with temporary data when your processor and memory are powered down? A retention register and memory-cell combination is one option, though this will lead to some power leakage. An alternative is to store important data in non-volatile memory (NVM), rather than using leakage-prone SRAM and registers. NVM enables quick access to the data when you power your system back up.

As ever, though, making the right choices can be tricky: A process that’s set up to minimize leakage and supports high-density NVM might not deliver the performance that efficient, on-chip RF modules require. And if you then go for a discrete RF transceiver and factor in the energy needed to shift data to it, you’ll likely negate or even outweigh the power savings you’ve achieved by implementing on-chip NVM. Look carefully at your application’s requirements to decide which is the best approach for your custom SoC.

Active element optimization

Let’s not forget the components that generally need to remain active. Little details, such as whether you multiplex inputs into an analog-to-digital converter (ADC), affect the way you architect these circuits. For example, the trade-off that sigma-delta ADCs offer between energy efficiency, precision, and physical footprint may seem attractive. But this type of ADC isn’t suited to multiplexing; a successive approximation (SAR) ADC often performs better in this sort of use case. Modern SAR ADCs offer exceptionally low energy usage per bit per conversion (you’re looking at tens of femtojoules).

Don’t forget your front-end analog circuits, such as the buffers and amplifiers that condition signals prior to conversion. These see significant use and can require a lot of power. You can typically cut the energy both your ADCs and front-end circuitry use by optimizing things based on the amount of bandwidth and accuracy you need.

Tying it all together

Using power-aware design techniques will help you bring your subsystems together in an effective SoC, where circuits and subsystems activate when needed, and can be shut down without impacting areas that must remain operational.

Following standards – including the Unified Power Format (UPF) – can help, though attention to detail at various levels remains essential. Imagine two subsystems (A and B) that need to run concurrently. Physical limitations may dictate that A and B sit in a bigger power island that incorporates subsystems C and D, which aren’t needed when A and B operate. To ensure your SoC works, testing must make sure the full island powers up in the right way, without exceeding the power budget. If this isn’t possible, you may need to alter your power-control architecture, perhaps moving subsystems C and D to another power island.

Lastly, look out for on-chip noise, which could lead you to further improvements around your power islands. For example, you could use a low-noise low-dropout regulator to power independent mixed-signal sections, and once you’ve taken the measurement or communicated the data, switch to a more efficient DC/DC converter for analysis.

Custom ICs: Frequently the best option

These examples demonstrate some of the complexity and intricacy involved in optimizing energy efficiency in IIoT sensor nodes. In many cases, correctly designed custom integrated circuits are the best option, both in terms of cost and energy usage. Anyone designing sensor nodes for the IIoT should, therefore, ensure they have access to expertise around implementing mixed-signal ICs.

 

About the authors

IIoT sensor nodesO’Riordan is a Senior Staff Design Engineer at S3 Semiconductors.  He has over 20 years’ experience in the field of mixed-signal integrated circuits.  He has worked at ITALTEL prior to joining S3 Semiconductors in 1996.  Noel has a Bachelor of Engineering and Master of Engineering Science degree from University College Dublin, Ireland.  He is also an Adjunct Senior Lecturer in Electronic Engineering at University College Dublin.

 

IIoT sensor nodesTommy Mullane is a Senior Systems Architect at S3 Semiconductors.  He received the B.E. degree in Electronic Engineering from the National University of Ireland, Dublin (UCD) in 1997. He has worked in research in optoelectronic devices and received a Masters in Technology Management from UCD in 2006. From 2000 to 2014 he worked for a Dublin based start-up called Intune Networks — on next-generation optical Telecommunication systems, working in a variety of technical disciplines, from optics to chip design, software, and systems. He holds 5 patents and has published a number of papers.

 

Smartphone biosensor tracks heart rate, blood pressure, oxygen sat, and more

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MediaTek Inc. today unveiled MediaTek Sensio, the first 6-in-1 smartphone biosensor module. MediaTek Sensio is a powerful advanced health monitoring solution which makes it easy to track heart rate information, blood pressure trends, peripheral oxygen saturation levels and more. Available as an embedded module in smartphones, MediaTek Sensio makes it possible for consumers to quickly check and monitor physical wellness on a device they use most — their smartphone.

Smartphone biosensor“Giving people the power to access their health information with a smartphone is a major step in making the world a healthier place,” said Dr. Yenchi Lee, Sr. Director of Product Marketing for MediaTek’s wireless business. “With our MediaTek Sensio biosensor module and software, developers and device makers have a powerful, embedded health monitoring solution that delivers heart and fitness information in around 60 seconds.”

The MediaTek Sensio MT6381 is a comprehensive software and module solution designed specifically to deliver valuable health data, consisting of optical, electrical and processing components. The customizable, compact solution means device manufacturers have the flexibility to embed the MediaTek Sensio module directly into all types of smartphones, versus using multiple sensors. With MediaTek Sensio, manufacturers are able to develop proprietary applications or leverage third-party applications and developer add-ons.

The module uses light emitting diodes (LEDs) in conjunction with a light sensitive sensor to measure the absorption of red and infrared light by the user’s fingertips. By touching a device’s sensors and electrodes with your fingertips, MediaTek Sensio creates a closed loop between your heart and the biosensor to measure ECG and PPG waveforms. Watch how MediaTek Sensio works.

Sensio delivers these six key health data points in about 60 seconds:

  • Heart-rate — MediaTek Sensio measures heart beats per minute.
  • Heart-Rate Variability — MediaTek Sensio measures variation in the time between heartbeats.
  • Blood Pressure Trends — MediaTek Sensio measures blood pressure trends so users can see a range of data over a period of time.
  • Peripheral Oxygen Saturation (SpO2) — MediaTek Sensio measures the amount of oxygen in the blood.
  • Electrocardiography (ECG) — MediaTek Sensio measures the electrical activity of the heart over a period of time and displays it in graph form.
  • Photoplethysmography (PPG) — MediaTek Sensio measures the change in volume of blood.

The first 6-in-1 total hardware and software solution, consisting of optical, electrical and processing components, delivers a package of smart health solutions that will help users to be more informed about their fitness levels.

MediaTek Sensio MT6381 includes:

  • Integrated R and IR LEDs for reflective PPG measurement + 1-channel ECG analog front-end
  • Compact 6.8 mm x 4.93 mm x 1.2 mm OLGA 22-pin package
  • Total External BOM: 4 caps + 2 electrodes
  • I2C /SPI digital interface

MediaTek Sensio will be available beginning in early 2018.

Microcontroller Top Talks in October on EDABoard.com forums

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(editor’s note: Intrigued by the problem? Have a question or another solution? Then click the “Read more” link and follow the conversation on EDAboard.com or log in to EDAboard and participate in the microcontroller forum threads.)

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My PIC microcontroller is also connected to an 16×2 LCD to display current mode. Everytime I change the mode to INT, the result only reflects after one full cycle. Is there any way to make it change right after I press the INT button? Read more

Behavior for 3.3v PIC and 5v display -I am using one display that works on 5 V and the interface is UART. The PIC16F886 runs on 3.3 V. What is the behavior if we interface both on UART? Read more

Shift register not working – This is my circuit and I programmed it to display the number 7 segment display.I can get the output but I can see the bits shifting while trying to display the numbers. Is there any error in my program or circuit? Read more

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UART receive string from SIM808 module –  I am using a SIM808 module in my application. How do I receive the string effectively? Is this a right way to receive the string? Read more

Problem in T6963C with 8051 – I am interfacing a T6963C with an AT89s52 with an external character mode (value is 88h). My data is not showing in glcd. Read more

Problem with design ESP8266 – I designed a circuit with an ESP8266, but the contactor circuitry (made up of a TRIAC, optoelectric and ULN2003) is not compatible. When you turn off the power, you must first re-insert ESP8266. Why? Read more

Controller hanging up – The concept of my project is to warn the people in my factory of their interval times. It will create sound when switched on by the operator. The relay output is connected to DC12V horn to create the warning.  My problem is when I switched on the circuit, the controller hung. It produced warning sound by continuous sound instead of beep sound (like LED blinking). I don’t what the problem is with the circuit and program. Read more

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Switches to control two LEDs –
1. Does this program control two LEDs?
2. Is it efficient program or it can be better ? Read more

 

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Fixed point vs Floating point


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Various types of processors (DSPs, MCUs, etc.) have the ability to do math using floating point numbers, but what exactly does this mean? In general, floating point math offers a wider range of numbers and more precision than fixed point math. Knowing the difference, and when to use which type of math can make a difference in terms of a faster calculation or a more precise calculation. Mostly, the objective is to use only as much calculating power as you will need to get the job done.


Figure 1: The number 0.15625 represented as a single-precision floating-point number per the IEEE 754-1985 standard. (Credit: Codekaizen, wikipedia.org)


A fundamental difference between the two is the location of the decimal point: fixed point numbers have a decimal in a fixed position and floating-point numbers have a sign. Both types of numbers are set up in sections, and there’s a placeholder for every portion of a number. Referring to Figure 1, fixed point numbers have a certain number of reserved digits that are on the left side of the decimal for the integer portion of the number. The numbers to the right of the decimal point are reserved for the fractional part of the number. If your MCU only uses fixed numbers, the decimal stays in the same place in that if two digits are set for the fractional portion, then that is the level of precision you will have going forward.


Figure 2: The decimal is called a “radix” in computer science terminology. The radix is set so there’s a fixed number of bits to the left and right of the radix. The number n would be the number of bits the processor can handle, so n could be 4,8,16, 32 or higher, depending on the bit width of the processor’s data path.


Very large numbers and very small numbers will have to fit in the same number of placeholders, what is actually bits, separated by the decimal in the same place, regardless of the number. For instance, if a fixed-point format will represent money, the level of precision might be just two places after the decimal. The programmer, knowing the register need hold only two bits after the decimal point, can put in 9999 and know that the fixed-point unit will interpret that number as 99.99, which is $99.99. (Here, base-10 numbers are used as an example, but recall that processors use base-2 or binary numbers).


Similarly, the number 001 would be interpreted by the code as 0.01. Decimals are left out of the code itself. Using the above money example again, the number 100 would be seen by fixed-point math as 1.00. The code for a fixed-point processor is written with respect to the decimal, which is in a fixed position. Fixed point math, independent of processor speed, is easier to code with and faster than floating point math. Fixed point is adequate unless you know that you will be dealing with higher numbers than the fixed-point unit can handle. Fixed-point numbers often are set up to use the most significant bit to represent a positive or negative sign. This means that a 4-bit unsigned integer has a range of 0 to 15 (because 24 = 16), while a 4-bit signed integer has a range of -8 to 7 (-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7). Again, this is because, in a number that has only 4 bits in which to represent it, there are only 16 total possible numbers that can be represented. (I.e., 24 = 16, where 4 is the total number of bits wide that the processor can handle in this example). Some recommend to never store money as a floating-point value.


Floating point numbers also fit into a specific pattern. In fact, the Institute of Electrical and Electronics Engineers (IEEE) has a standard for representing floating-point numbers (IEEE 754). A floating-point number doesn’t have a fixed number of bits before and after a decimal. Rather, a floating-point number is defined by the total number of bits reserved for expressing a number. Like fixed-point numbers, floating point numbers have a pre-determined number of bits to hold the floating-point number, which has a sign (positive or negative number) as well as a number (i.e., mantissa) with an exponent. All of this has to fit in the data path allotted for the processor, which could be 16-bit, 32-bit, or 64-bit, etc. (See Figure 2 for how a 32-bit wide floating point number might be expressed.) Floating point numbers store as many precision bits as will fit in the data path, and the exponent determines the location of the decimal point in relation to the precision bits. The length of the exponent and mantissa would reflect the largest and smallest numbers anticipated by the application.


Figure 3: IEEE 754 32-bit ( a.k.a. single precision) floating-point numbers have three parts: the sign, the exponent, and the fraction. The fraction is also known as a significand or mantissa. The signed bit is 0 for a positive number and a 1 for a negative number in this standard, with an 8-bit exponent. “Double precision” is 64-bits wide.


Floating-point numbers lose precision in that they only have a fixed number of bits with which to express a real number (e.g., 16-, 32- or 64-bit). Real numbers can go on to positive or negative infinity, and there is an infinite number of real numbers between 0 and 1, as well. A 16-bit processor has only 16-bits with which to represent numbers and is therefore capped at 216. For example, a 4-bit processor has only 4 bits in which to represent numbers and is capped at 9999 as its highest number (if it doesn’t use one bit for a sign). A 16-bit processor can only represent 216 different numbers.


Floating point numbers can seem confusing and complicated, but it’s also time-consuming for a processor. Doing math using floating point numbers can involve several steps to account for differences in exponential values. The IEEE 754 standard, first published as late as 1985, resolved problems having to do with creating portable code with respect to floating point conventions. Prior to the standard, companies handled floating point math as they saw fit, making code difficult to port from one type of processor architecture to another. The latest update to the standard was made in 2008. Several java-script based online tools are available for helping with understanding IEEE-754 floating point numbers using base-2. (Search for “IEEE-754 converter”.) Many articles and white papers have been written about how to best use floating point numbers since processors can be quite literal in comparing numbers and overflowing the highest possible number is going to roll the number over to zero. Simply put, floating point numbers can be much more complicated than fixed numbers with regard to how processors handle them.


 


 


DEMUX, MUX, and Decoders: How To Expand I/O


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The relentless march of technological progress has given engineers increasingly smaller and more energy efficient microcontrollers to use in their designs. These benefits do come with a cost, however. Physically smaller packages have less room for I/O pins meaning fewer peripheral components can interface with the microcontroller itself. Fewer peripherals means less functionality which tends not to be a desirable tradeoff.


Even when utilizing bus-based protocols such as I2C or SPI, there is often a need for each external integrated circuit to have a pin dedicated for chip select or output enable (often notated as CS or OE on schematics, or /CS and /OE for active low variations). After accounting for power, ground, reset, and the I2C pins on a small 8-pin chip like an ATtiny85, a design might at most interface with three external peripherals using the remaining I/O pins. Of course, one option would be to explore larger chips within the same microcontroller family. Depending on component availability or design constraints this might not be a possible option. Another possibility is to incorporate an additional circuit that sits between the microcontroller and the various external components. Circuits such as multiplexers, demultiplexers, and decoders come in a variety of packages and voltage levels so they can be incorporated into a board layout with relative ease.


Figure 1A: Demultiplexer can route a data output pin to different components based on address pins. Figure 1B: A decoder takes address pins as inputs and raises the corresponding pin to a logic high. Figure 1C: A multiplexer takes inputs from multiple devices, selected using the microcontrollers address pins, and routes the desired components output to a single input pin on the microcontroller.


With a demultiplexer we can take two of the microcontroller’s I/O pins and turn them into address pins (for example A1 and A0). The third pin serves as a digital output whose signal then can be redirected to up to four external peripheral components by toggling the address pins into one of four states including < A1:A0 > = 00, 01, 10, and 11.


If there is no need for a controllable output signal then it might be more desirable to instead use a decoder. With a decoder those same three pins (the two address pins and the digital output pin) could be instead used to interface with eight peripheral components thanks to the power of binary arithmetic (23 = 8). This is extremely useful in situations such as handling chip select or output enable pins of external ICs where those pins only need to drive to the source voltage or ground. Inverters can be placed on the output of the active high decoders to handle chips that required active low enables. Practically speaking 2:4 and 3:8 decoders are most common in discrete packages. However, it is possible to cascade multiple discrete decoders into larger networks as needed. Be careful not to go too large as problems may arise from fan-in and fan-out. Issues that could arise include slowed response times or even voltage levels dropping below defined logic levels.


Lastly, it is also possible to employ a similar concept for inputs being fed into a microcontroller from external devices such as sensors or switches. Instead of a demultiplexer, a multiplexer can be employed to funnel multiple outputs into a single input pin. Special care must be placed by the firmware designer to ensure the logic is correct when handling the different inputs and the associated variables that represent them in code. Be aware that decoder, multiplexer, and demultiplexer chips may have output enable (OE) pins themselves. Depending on the circuit design these pins can be hardwired to ground or source voltage so a microcontroller pin need not be used. The tradeoff being the chip is always on which may or may not be desired. Otherwise, a microcontroller pin must be budgeted for in the design.


Top microcontroller threads on EDAboard.com – August


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(editor’s note: Intrigued by the problem? Have a similar challenge? Have a question or another solution? Then click the “Read more” link and follow the conversation on EDAboard.com or log in to EDAboard and participate in the microcontroller forums.)


PWM using Controller – I  working on one project which requires the following condition: Analog voltage and PWM on the same pin as the microcontroller. Is this possible? Currently I am using one pin of microcontroller. Read more


Sensored BLDC motor issue – I am developing a driver which is has a max current protection 20A. The motor is driving on 12V and 24V. The motor is a 3-phase BLDC motor. My driver gives motor speed as 1800 RPM at 24V, 1.3A without load, and 900 RPM at 12V, 0.9A without load. I have checked the other drivers which have dedicated IC in the circuitry for BLDC motors. They are giving the following speeds,


2000 RPM at 24V , 1.5A current

1100 RPM at 12V, 1.1A current


My project is to change those dedicated ICs with a microcontroller. I have implemented and its working fine. All functionalities are working fine. But the project is not acceptable because of speed characteristics. Read more


Ethernet communication using microcontroller – I want to make a device that will send a link to a local host via LAN/Ethernet. The host PC is connected with the device via LAN cables, switches/routers, and there will be over 100+ same devices which are doing the same. In this case how the system should be arranged?  Does it need to give each device a IP address for each? And how these devices will send the data to the main PC or local host? Read more


Problem on UART PIC16F628A Tx – Rx – I’m having a problem adding a button. There is no an error (except I place UART2_Read), but I can’t add more buttons on PORTA.F1 (Tx) and Led PORTB.F4 (Rx). Read more


Two keys (0 or 4) pressed at same time – What happens when in color key 0 and key 4 are pressed and held. What display behavior will be affected? Read more




Current protection issue in BLDC motor – I am developing BLDC motor driver with 24V ,20A current.  Suppose, the motor is at full load and POT (Throttle) is at maximum and then the motor is trying to start and somebody picks rotor by hand then the motor stops. It should reach 20 A and then it should stop as 20A set as current protection range. But it is stopping at 1 A or 2 A of current. Read more


5 µsec delay using PIC12f675 not working – I am using a PIC12f675 with a 20 Mhz clock and a PIC12f675 with 20 Mhz clock I want to generate a 5 µs delay. I calculate by using this formula:

Pic input frequency= Fosc / 4= 20 Mhz / 4 = 5 Mhz

Prescaler = 1:4

Tick Counter frequency = Prescaler/5 Mhz = 4 / 5 Mhz = 0.8 μs

Delay required =5 μs

Delay required = Timer Count * Tick Counter frequency

by using this formula timer count is 249. Read more


dsPIC33f internal Flash as EEPROM – For my application a 16-bit  dsPIC33FJ64GS606 microcontroller. The controller doesn have an EEPROM option. I found an option to use Program memory as for EEPROM from the Microchip website. I got Project file but it cannot compile it. Read more


Concatenating bytes into a 32-bit word – I’m comparing two methods for concatenating received UART bytes into 32-bit words. Method #0 uses unions Method #1 – uses shifting Although both of the above work, I’d like to know which one do you find better to use and why? Read more


How to implement a lookup table in C programming? In one of my applications, I need to use a lookup table in C. I need to pick the data depending on two variable parameters —temperature and pressure. For example, if temp=0 and pressure=750, then I have to pick 14.37.and so on. Please see the attached table. Read more




Memory technology from Floating Gates to FRAM


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There are two basic types of memory: volatile and non-volatile. Volatile memory loses its content and becomes a blank slate whenever power is completely removed. However, volatile memory doesn’t need much power and can maintain its contents with a small battery. Non-volatile memory retains its contents even if power is completely removed.


SRAM and DRAM

Volatile types of memory include Static RAM (SRAM) and Dynamic RAM (DRAM), which are in wide use as working memory for CPUs. SRAM is reliable and fast, with access times from 10 to 30 ns.  DRAM access time is typically 50 – 60 ns. DRAM uses capacitors and needs to be refreshed as the capacitors used to store data lose charge over time. SRAM does not require refresh, but like DRAM needs a constant power supply to avoid losing stored data. DRAM is typically used as the main working memory for the CPU in a computer, whereas SRAM is used for caches and other applications needing high-speed registers.


NVRAM

A synopsis of types of Non-volatile Random Access Memory (NVRAM) follows:


Technically non-volatile memory, punch cards were the earliest mainstream form of storing data on media, followed by magnetic tape and floppy disks. The floating gate memory cell was the first instance of NVRAM. Floating gates are transistors that hold one bit (0 or 1) of memory by either holding a charge or not.


The difference between EPROM and EEPROM

An EPROM (Erasable Programmable ROM) can be written to but needs to be exposed to UV light through a window in the package in order to be erased. In wider use today is the Electrically Erasable Programmable ROM (EEPROM) chips, which are re-writeable integrated chips (ICs) that keep data when power is removed and erase data with an electrical signal. In order to write to an EEPROM, you have to erase it first. EEPROMs can be addressable by the bit or the byte (8 bits), so different lengths of data can be retrieved. EEPROMs are most often used for storing small amounts of onboard data, such as boot code.


ROM, PROM, FROM, and OTP NVRAM

Another type of non-volatile memory is Read Only Memory (ROM), which includes Programmable Only Memory (PROM) which is programmable once after manufacture and locked by way of a fuse; Field Programmable Memory (FPROM), which is also programmed after manufacture; and One-Time Programmable Non-Volatile Memory (OTP NVRAM), which is an EPROM without a window for UV exposure and erasure, which reduces cost.


Figure 1: A chart showing the various memory technologies and their relationships. The chart is not comprehensive but covers those mentioned here.  (Source: Author)


Flash Memory

Arrays of floating gates in either a logical NOR or NAND arrangement make flash memory. Flash memory shares many of the same technical attributes as EEPROM. However, Flash can retrieve entire blocks of memory at a time, whereas EEPROMs can only retrieve bits or bytes with each fetch instruction. Flash memory is typically used to store large amounts of data from devices such as digital cameras and is also used as a faster replacement for a computer hard drive (HDD). NAND Flash-based memory is used to replace traditional hard drives as primary storage on computers as a solid-state drive (SSD). There are two types of flash memory: NAND and NOR.  NAND flash technology can read faster than it writes and is more can fit in the same area than NOR-based flash. Flash memory has become portable with USB memory sticks, SD cards, and other interface technology that are used to access flash.


Newly emergent NVRAM

New NVRAM technologies have appeared in shelves in just the past decade or so. Ferroelectric Random Access Memory (FRAM, F-RAM, or FeRAM) is another non-volatile memory technology that writes extremely fast, has high endurance, and is power efficient. According to Texas Instruments, “The actual write time to a FRAM memory cell is less than 50 ns. That is approximately 1000x faster than EEPROM. Additionally, unlike EEPROM where you must have two steps to write data: a write command, followed by a read/verify command; FRAM’s write memory function happens in the same process as reading memory. There is only one memory access command, one step for either reading or writing.” FRAM also uses on the order of 1.5 V versus the 10-14 V that EEPROM requires.  FRAM is also reliable and has a R/W endurance of up to 100 trillion cycles. FRAM is also secure because it’s more resistant to data corruption from outside influence and has the same power consumption signature for a read as it has for a write.  FRAM is not affected by magnetic fields. FRAM is actually fairly radiation-resistant compared to others. Therefore, FRAM is quickly becoming a favorite in medical and automotive industries.


MRAM (magnetoresistive random access memory) is an NVRAM technology that stores data using magnetic state. MRAM is vulnerable to external magnetic fields, however external shielding of the MRAM at the package level mitigates hazards related to exposure.


What is the difference between FRAM and MRAM?

Everspin Technologies is a primary producer of MRAM. According to Everspin, “MRAM or Magnetic Random Access Memory uses a 1 transistor – 1 magnetic tunnel junction architecture with the magnetic “state” of a ferromagnetic material as the data storage element. Because MRAM uses a magnetic state for storage (rather than charge which can ‘leak away’ with time), MRAM offers significantly long Data Retention (+20 years) and unlimited endurance.”[i] Everspin uses standard CMOS technology to produce MRAM. It’s as yet unclear whether MRAM or FRAM will become dominant as prices come down over time. Until then, low-cost flash memory (such as NAND) will retain prominence in SSDs, USB thumb drives, and SD cards.


Figure 2: Low-power MRAM uses magnetic switching, which requires no displacement of electrons. Thus, there’s no mechanism to cause wear-out, resulting in unlimited endurance. MRAM boasts 20-year data retention time without power and a 35 ns read cycle. (Source: Everspin Appnote “Comparing Technologies: MRAM vs. FRAM)


Future memory technologies

Future memory technologies, or memory technologies that provide promising research, include spin-transfer torque random-access memory (STT-RAM), phase-change memory (PCM), and resistive random-access memory (RRAM). MRAM and FRAM are very new and doubtless, have improvements to come. Memory technology is also being explored with the possibility of memristors. New classes of memory, already under research and development, may someday include plastics, quantum dot memory, three-dimensional memory, and organic/biological based memory.[ii]


[i] Bohac, Chuck. Comparing Technologies: MRAM vs. FRAM . 2013, pp. 1–7, Comparing Technologies: MRAM vs. FRAM .


[ii] Meena, Jagan Singh, et al. “Overview of Emerging Nonvolatile Memory Technologies.” Nanoscale Research Letters, Springer, 25 Sept. 2014, .