by Matthew Ballance, Mentor, a Siemens Business Register tests are a very useful smoke test at all design levels — from IP to subsystem to SoC. While the built-in register-test sequences in the UVM library are useful at the IP level, capturing register-test intent in a PSS model makes register-test functionality portable from the IP […]
Retargeting existing tests in an integrated SoC verification flow
by Matthew Ballance, Mentor, a Siemens Business The raison d’etre for portable stimulus is reuse. The Accellera Portable Stimulus Standard (PSS) promotes test intent reuse throughout the verification process and across the multiple engines on which those verification runs are performed. Test intent captured as portable stimulus models enables test reuse from the IP to […]
Finalists announced for inaugural Embedded Computing category in LEAP Awards
Three finalists were announced for the inaugural LEAP Awards’ Embedded Computing Category, comprising innovative products and technologies. The competition was scored by a panel of independent technical/engineering-oriented judges. Responsible for the Embedded Computing category were these four judges: Plamen Doynov Research Professor University of Missouri-Kansas City Plamen Doynov became a research professor in physics last […]
EDA, Spice software supports TSMC 7-nm FinFET Plus, 5-nm FinFET processes
Mentor, a Siemens business, today announced certification for TSMC’s 7nm FinFET Plus and the latest version of 5nm FinFET processes for its Mentor Calibre nmPlatform and Analog FastSPICE (AFS) Platforms. In addition, Mentor continues to expand features of both the Xpedition Package Designer and Xpedition Substrate Integrator products supporting TSMC’s advanced packaging offerings. Mentor Calibre nmPlatform for TSMC 5nm and 7nm FinFET Plus […]
Design tool generates photonic layouts for fabrication
Mentor, a Siemens business, today announced LightSuite Photonic Compiler – the industry’s first integrated photonic automated layout system. This new tool enables companies designing integrated photonic layouts to describe designs in the Python language, from which the tool then automatically generates designs ready for fabrication. The resulting design is “Correct by Calibre” – with the […]
HLS flow software now handles FPGA components
Achronix Semiconductor Corporation announced availability of an optimized High-Level Synthesis (HLS) flow from its partner, Mentor, a Siemens business, for its FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor’s Catapult HLS and Achronix’s ACE design tools. Initially used for 5G wireless applications to reduce the overall development […]
Physical IC verification tool optimizes ASICs, SoCs
Mentor, a Siemens business, today announced Calibre® RealTime Digital – a new physical verification tool that works in concert with popular commercial place-and-route environments to ensure “Correct-by-Calibre” routing, and help design teams cut weeks off of IC signoff. Calibre RealTime Digital is the sister product to Mentor’s multi-award-winning Calibre RealTime Custom tool introduced in 2011 […]
Chip design tools now handle TSMC 5 and 7-nm FinFET IC processes
Mentor, a Siemens business, has announced that several tools in its Calibre nmPlatform and Analog FastSPICE (AFS) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. Mentor also announced it has updated its Calibre nmPlatform tools in support of TSMC’s Wafer-on-Wafer (WoW) stacking technology. These Mentor tools and TSMC’s […]
Emulation platform handles up to 1.25 billion gates for data center designs
Mentor, a Siemens business, today introduced the Veloce® StratoT, which expands the footprint choices and configuration options available from its Veloce Strato™ emulation platform family. The Veloce Strato platform is a third-generation, data-center friendly emulation platform, and the only emulation platform on the market with full scalability across both software and hardware. In addition, the […]
Chip design CAD software supports integrated fan-out advanced packaging, chip-on-wafer-on-substrate packaging technologies
Mentor, a Siemens business, today announced several enhancements to its Calibre® nmPlatform, Analog FastSPICE™ (AFS™) Platform, Xpedition® Package Integrator and Xpedition Package Designer tools in support of TSMC’s innovative InFO integrated fan-out advanced packaging and CoWoS® chip-on-wafer-on-substrate packaging technologies. The TSMC InFO and CoWoS 3D packaging technologies enable customers to mix multiple silicon dice on a single device and […]
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