To help integrated circuit (IC) designers achieve design closure faster, Mentor, a Siemens business, today announced the extension of their powerful Calibre Recon technology to the Calibre nmLVS circuit verification platform. Introduced last year as an extension to Mentor’s Calibre nmDRC suite, the Calibre Recon technology is designed to enable customers to rapidly, automatically and accurately analyze IC designs for errors during early-stage verification design iterations, enabling significantly shortened design cycles and faster time to market.
The Calibre nmLVS-Recon solution helps speed overall circuit verification turnaround time by helping system-on-chip (SoC) engineers, circuit designers, and IC circuit verification teams identify and resolve selected systemic errors early in the development phase. These types of violations can consume valuable compute resources and potentially generate millions of error results, many of which are due solely to the incomplete status of the design. Early adopter customers leveraging the Calibre nmLVS-Recon solution realized more than 10x runtime improvements and 3x less memory requirements when analyzing early-stage designs.
The Calibre nmLVS-Recon technology is based on a flexible configuration framework that enables multiple-use models, allowing design teams to select and analyze specific classes of circuit verification issues. The tool features automated, intelligent execution heuristics engineered to help users seamlessly navigate between a complete Calibre nmLVS signoff flow and Calibre Recon selected circuit verification checks. With advanced options for data partitioning, design breakdown, data reuse, task distribution, and error management, the Calibre nmLVS-Recon flow can be used with any foundry/integrated device manufacturer’s (IDM) Calibre sign-off design kit “as is”, and on any process technology node.
Early design versions typically contain many gross systemic violations. For example, a “shorted nets” class of violation generates millions of errors and is very compute-intensive. Circuit verification engineers can use the Calibre nmLVS-Recon short isolation configuration to interactively and iteratively find and fix these types of violations quickly and efficiently. This option is built-in, allowing optimal flexibility and variation in the design analysis intent, while maintaining ease of use and seamless use model transition.
The Calibre nmLVS-Recon initial offering will be available to the market with the Calibre family release in July of 2020, with planned additional capabilities in later releases.