CEVA introduced a new lightweight, multi-purpose, processor IP core to streamline the design of cellular-enabled low data rate industrial and consumer loT devices. The CEVA-X1 IoT processor deploys a single-core DSP+CPU architecture, specifically designed to address the severe size, power and cost limitations demanded for deploying the latest LTE Cat-M1 (formerly eMTC) and Cat-NB1 (formerly NB-IoT) standards as well as future FeMTC and 5G cellular IoT use cases.
The connected cellular IoT market is expected to explode in the coming years, with ABI Research predicting the Cat-NB1 standard will account for more than one third of all cellular IoT shipments – a value which is greater than legacy M2M or the current Cat-1 standard. End markets and applications where these technologies will be deployed include the smart home, smart utilities, asset tracking, wearables, health, security and environmental, industrial and agricultural monitoring and control.
The CEVA-X1 also serves as a multi-purpose, multi-mode processing hub for a range of tightly-associated IoT workloads, including Wi-Fi 802.11n, 802.11ac, Bluetooth/BLE, Zigbee/Thread, LoRa, SIGFOX, narrowband voice, GNSS and sensor fusion. Crucially, the CEVA-X1 can handle multiple processing workloads simultaneously, allowing developers complete flexibility to tailor their system to meet the requirements of any IoT use case.
The latest core derived from the NEW CEVA-X architecture framework, the CEVA-X1 employs an extended Instruction Set Architecture (ISA) that, in addition to DSP processing, also allows it to efficiently handle CPU software workloads, such as protocol stack and system control. Comparing EEMBC® CoreMark® scores, a commonly used benchmark to measure the performance of CPU processing in embedded systems, the CEVA-X1 CoreMark/MHz score of 3.3 is on par with the most commonly used CPU for IoT stacks – the ARM® Cortex™-M4 – which achieves a CoreMark/MHz score of 3.4. This effectively eliminates the requirement for a separate CPU core in the system when using the CEVA-X1, providing significant cost, power consumption and ease-of-programming benefits of a single-core approach.
The CEVA-X1 also enables further differentiation through CEVA-Connect, its advanced system control interface to offload the processor using dedicated control and data plane hardware, and automate traffic management between the CEVA-X1 and CEVA or customer proprietary hardware accelerators such as the Cat-M1 Turbo decoder.
