Synopsys is now making available a validated built-in-self-test (BIST) and repair IP to enable designers to achieve the most stringent levels of functional safety for automotive system-on-chips (SoCs). The complete solution includes the ASIL D Ready Certified DesignWare STAR Memory System, STAR Hierarchical System, and DFTMAX LogicBIST software qualification kit, as well as ARC HS processors, providing test and repair of memory and logic blocks with automatic test integration and validation of analog/mixed-signal IP. By providing a pre-verified functional safety test solution, Synopsys is helping designers ensure high test coverage, achieve low defective parts per million (DPPM), and reach the required automotive safety integrity levels (ASILs) of their automotive designs.
“Safety critical automotive SoCs need to control run time scheduling, manage switching activity, and monitor the status of the logic and memory BIST,” said Christophe Eychenne, DFT architect at Bosch. “Synopsys’ ASIL D Ready Certified functional safety test solutions can fully support our requirements for high detection of logic and memory faults, self-test power up, and mission mode testing of our ADAS SoCs.”
Synopsys’ functional safety test solution leverages an industry-standard IEEE1500/1687-based infrastructure to reduce integration risk and offers multiple configurations to balance SoC test time, floor planning challenges, and system constraints. The solution includes complete test and repair capabilities for on-chip and CPU/GPU memories, logic blocks, and analog/mixed signal IP:
- DesignWare STAR Memory System offers memory BIST and repair capabilities with support for early silicon debug and in-field diagnostics using algorithms optimized for FinFET-specific transistor defects. Advanced STAR error correction code (ECC) circuitry detects and corrects single-bit and multi-bit upsets to improve reliability during in-system operation.
- DFTMAX LogicBIST software qualification kit provides a synthesis-based solution for rapid in-system self-test of digital circuits, enabling design teams to converge quickly on quality, cost goals, and functional safety requirements.
- DesignWare STAR Hierarchical System ensures high coverage using hierarchical test for IP block integration and enables re-use of IP patterns. Automatic test integration and validation with dynamic test scheduling optimize test time and power consumption, even post silicon. The STAR Hierarchical System detects process variation and device aging (soft monitoring) with its on-chip Measurement Unit feature.
- DesignWare ARC HS processor selects and activates tests by functioning as an on-chip safety manager. The interface between the ARC HS processor and other solution components has been optimized and validated to enable initiation and scheduling of the BIST activities and can be fully controlled by system software.
The STAR Memory System, STAR Hierarchical System, DFTMAX LogicBIST and ARC HS processor family are available now.
More information: Synopsys, 185 Berry St #6500, San Francisco, CA 94107; (415) 321-5200.
- View the webinar: Addressing Functional Safety in SoCs with Test Solutions
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