Chipset for clocked DDR5 client modules pushes the ceiling to 9600 MT/s

Pushing DDR5 beyond 6400 MT/s introduces signal degradation, clock jitter, and timing instability severe enough to require a different architecture. The industry’s fix is to move clock conditioning onto the module itself. The CUDIMM/CQDIMM (desktop) and CSODIMM (laptop) form factors embed an on-module client clock driver that conditions and redistributes the clock signal locally, rather than relying on a clean signal to survive the full trace from CPU to DRAM.

Rambus released a three-chip set covering everything a module vendor needs to build these clocked DIMMs. The CKD02 retimes and conditions the module’s clock. The PMIC5120 handles voltage step-down for the DRAM and active chips. The SPD Hub manages module identification and telemetry. Together, they support clocked DDR5 from 8000 to 9600 MT/s.

Having one vendor supply all three chips simplifies validation, including power sequencing, timing margins, and SPD communication are designed together rather than integrated piecemeal. Rambus previously supplied interface chips for server RDIMMs; this now brings the same signal-integrity approach to the client tier.