The Silicon Labs Si5391 is said to be the industry’s lowest jitter, any-frequency clock generator. It can provide all clock frequencies needed in 200/400/600G designs from a single IC while delivering sub-100 fsec RMS phase jitter performance for 56G SerDes reference clocks. Featuring up to 12 differential outputs, the Si5391 clock is available in frequency flexible A/B/C/D grade options. A Precision Calibration P-grade option optimizes RMS phase jitter performance with a 69 fsec (typical) specification for the primary frequencies needed in 56G SerDes designs. The Si5391 is a true sub-100 fsec “clock tree on a chip” solution designed to synthesize all output frequencies from the same IC while meeting 56G PAM4 reference clock jitter requirements with margin.
The Silicon Labs Si539x jitter attenuators are designed to meet the exacting specifications and high-performance requirements of internet infrastructure. These ultra-low-jitter clocks reduce cost and complexity for a wide range of timing applications. Si539x any-frequency jitter attenuating clocks generate any combination of output frequencies from any input frequency while delivering industry-leading jitter performance (90 fsec RMS phase jitter). Si5395/4/2 P-grade devices offer best-in-class jitter (69 fsec RMS typical phase jitter) for 56G/112G SerDes clocking applications.
The new Si56x Ultra Series VCXO and XO family is a candidate for next-generation high-performance timing applications requiring ultra-low-jitter oscillators. Si56x VCXO/XOs are customizable to any frequency up to 3 GHz, supporting twice the operating frequency range of previous Silicon Labs VCXO products with half the jitter. The Si56x oscillators are available with single, dual, quad, and I2C-programmable options in industry-standard 5×7 and 3.2×5-mm packages, enabling drop-in compatibility with traditional XO, VCXOs and VCSOs. This family features devices with typical phase jitter as low as 90 fsec.
Silicon Labs also offers the Si54x Ultra Series XO family for applications requiring tighter stability and guaranteed long-term reliability, such as optical transport networking (OTN), broadband equipment, data centers and industrial systems. The Si54x XOs are purpose-built for 56G designs, which rely on four-level pulse-amplitude modulation (PAM4) signaling for serial data transmission to increase the bit rate per channel while keeping the bandwidth constant. Using an Si54x XO as a low-jitter reference clock maximizes signal-to-noise ratio (SNR) headroom, minimizes bit errors and enhances signal integrity. The Si54x family offers best-in-class performance, with typical phase jitter as low as 80fs.
These timing products are priced (USD) in 10,000-unit quantities as follows:
Si5391 clock generator – from $6.05
Si539x jitter attenuating clocks – from $6.60
Si56x XO/VCXOs – from $5.21
Silicon Labs provides a wide range of evaluation boards (EVBs) to accelerate device evaluation and development. Clock and oscillator EVB pricing ranges from $95 to $299 (USD MSRP). The Si5391 and Si539x families are supported by Silicon Labs ClockBuilder Pro (CBPro) software. Customers can tailor a clock solution to their specific requirements using CBPro and receive samples as soon as two weeks.
Silicon Labs, 400 W. Cesar Chavez, Austin, TX 78701 USA, www.silabs.com/56G.