DDR design IP will handle 16-nm FinFET chips

Cadence Design Systems, Inc. has announced that it is updating its leading-edge, high-speed SerDes communication interfaces and low-latency Denali DDR memory IP solutions to support TSMC’s 16nm FinFET Compact (16FFC) and 28nm HPC Plus (28HPC+) process technologies. These key design IP solutions for TSMC’s 16FFC and 28HPC+ processes can help reduce time to market for customers designing advanced Systems-on-Chip (SoCs).

Cadence provides design IP for a wide array of industry standards such as DDR, PCIe, MIPI, Ethernet, USB, DisplayPort, and 802.11. Delivery of IP for 28HPC+ process technology will begin with Denali DDR memory IP in Q2 ’16, and IP for the other standards in Q4 ’16. Delivery of IP for the 16FFC process will begin with 16Gbps SerDes IP in Q3 ’16, and IP for the other standards in Q4 ’16.

 Cadence

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