Legato eliminates the complexity of piecing together point tools for multiple design and verification tasks and can lead to productivity gains of up to 2X when compared with previous point tool offerings, according to Cadence. The Legato Memory Solution’s cohesive design environment automates design steps and lets customers use the innovative Cadence toolset to deliver products to […]
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ARM design environment aids development of mixed-signal IoT designs
Cadence Design Systems, Inc. today announced expanded support for the enhanced ARM® DesignStart™ program, including the newly added ARM Cortex®-M3 processor and the ARM CoreLink™ SDK-100 System Design Kit, which includes the fully verified CoreLink SSE-050 subsystem, enabling engineers to further accelerate the delivery of mixed-signal internet of things (IoT) designs. The Cadence® Hosted Design Solutions (HDS) design environment […]
Processor design simulator gives 5X better multi-core performance
Cadence Design Systems, Inc. announced the Xcelium™Parallel Simulator, the industry’s first production-ready third generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Cadence Xcelium […]
FPGA-based prototyping platform includes advanced memory modeling
Cadence Design Systems, Inc. announced the new Protium™S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity. The Protium S1 platform provides front-end congruency with the Cadence® Palladium® Z1 Enterprise Emulation Platform, thereby delivering 80 percent faster design bring-up on average when compared to typical FPGA prototyping approaches. Utilizing Xilinx® Virtex™ UltraScale™ FPGA technology, the new Cadence platform […]
DDR design IP will handle 16-nm FinFET chips
Cadence Design Systems, Inc. has announced that it is updating its leading-edge, high-speed SerDes communication interfaces and low-latency Denali DDR memory IP solutions to support TSMC’s 16nm FinFET Compact (16FFC) and 28nm HPC Plus (28HPC+) process technologies. These key design IP solutions for TSMC’s 16FFC and 28HPC+ processes can help reduce time to market for customers […]
WLCSP design package targets power-optimized wireless mobile devices
Cadence Design Systems, Inc. has announced the availability of the industry’s only foundry-proven IC packaging design and analysis solutions for advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs. The new capabilities enable the faster multi-chip integration that is ideal for smaller, lighter and power-optimized wireless mobile devices. This complete IC packaging design […]
Audio software framework for DSP-based SoCs
Cadence Design Systems, Inc. has announced the Cadence HiFi Integrator Studio, an audio software framework that provides OEMs and application developers faster time to market when integrating Tensilica HiFi DSP-based systems on chip (SoCs) into their products. This announcement also includes the first hardware integration into the Android Studio development platform. Cadence is scheduled to […]
Schematic capture package supports Intel Schematic Connectivity Format for Intel-based design reviews
Cadence Design Systems, Inc. has announced that OrCAD Capture now provides export capability for Intel Schematic Connectivity Format (ISCF), targeted at automating Intel-based design reviews. ISCF was developed by Intel to streamline the collaboration process with its customers. Intel worked with Cadence to develop a direct ISCF generation capability in OrCAD Capture to make this […]
Verification platform trims ARM boot-up time
Cadence Design Systems, Inc. (NASDAQ: CDNS) announced that ARM® utilized Cadence® Palladium® Hybrid technology and ARM Fast Models to achieve a 50X faster OS boot-up during the development of its ARM Mali™-T760 GPU. Compared to the previous emulation only solution, this resulted in up to 10X speed-up of overall hardware-software testing. This increased speed reduced […]
