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Xilinx snags LEAP Gold in Embedded Computing category

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The winners of the 2020 LEAP Awards (Leadership in Engineering Achievement Program) were announced last week in a digital ceremony, with products across 12 categories, including embedded computing, power electronics, and test and measurement. Critical to LEAP’s success is the involvement of the engineering community. No one at WTWH Media selected the winners. Instead, our editorial team did the arduous work of assembling a top-notch independent judging panel, comprised of a cross-section of OEM design engineers and academics — 14 professionals in total. This judging team was solely responsible for the final results.

Xilinx’s Adaptive Compute Acceleration Platform (ACAP) delivers AI inference and wireless acceleration with integrated AI engines that deliver over 100X greater compute performance than today’s server-class CPUs.

In the Embedding Computing category, Xilinx took home the gold with their Versal AI Core, the first Adaptive Compute Acceleration Platform (ACAP), is a multi-core, heterogeneous compute platform that dynamically adapts at the hardware and software level for a wide range of applications and AI workloads from edge to cloud. The platform integrates next-generation scalar engines for embedded compute, adaptable engines for hardware programmability, and intelligent AI Engines and DSP Engines for AI inference and signal processing.

The architecture is unique as it solves the most difficult problem of AI inference—compute efficiency—by coupling ASIC-class compute engines (AI engines) with adaptable hardware to implement custom memory hierarchy and custom neural network layers. Versal AI Core breaks through traditional compute bottlenecks, specialized hardware customization without manufacturing a new chip. The AI Engine delivers 8X the compute density at half the power of traditional FPGA solutions and delivers low-latency Convolutional Neural Network (CNN) execution 3.5X faster vs. traditional GPUs.

The adaptability and heterogeneous architecture of Versal AI Core is a key advantage over traditional AI accelerators that typically focus on a subset of AI workloads. AI algorithms are diverse across industries—from cloud computing to networking, to edge and autonomous system. The adaptable nature of Versal AI Core makes it applicable for a breadth of markets.

Commenting on the Versal AI Core, judges said: “A game changer for the next generation of networking electronics, medical imaging diagnostic instruments and any application needing state-of-the-art processing power.”

Picking up the silver award was Texas Instruments Jacinto 7 processor platform that brings enhanced deep learning capabilities and advanced networking to solve design challenges in ADAS and automotive gateway applications. The TDA4VM processors for ADAS and DRA829V processors for gateway systems are the first two devices in the portfolio. These devices include specialized on-chip accelerators designed to segment and expedite computer vision, deep learning and other data-intensive tasks, allowing the car to more accurately perceive and react to the world around it.

Supporting sensor fusion from cameras, LIDARs, radars and other sensors, the Jacinto 7 devices are able to accept inputs from multiple sources to not only create the most accurate vision of the world around the car, but also to utilize machine learning intelligence to help the car and driver best react to that world. Designed for L2 and L3 automated functions, these devices are targeted for applications ranging from automatic emergency braking and lane-keep assist to more accurate autonomous parking and highway autopilot.

Finally, the bronze went to Lattice Semiconductor for their CrossLink-NX FPGA, the FPGA developed on the Lattice Nexus FGPA platform, the industry’s first 28nm FD-SOI-based FPGA platform optimized for low power operation in a small form factor. The CrossLinkCrossLink-NX FPGA-NX FPGA provides the energy efficiency, small form factor, high reliability and high-performance developers in communications, compute, industrial, automotive, and consumer markets need to enable innovative embedded vision solutions for the Edge. These new chips are designed to address the latest trends in video processing: mixing multiple sensors and displays, higher resolution video, multiple interfaces, and Edge AI processing.

CrossLink-NX consumes 75 percent less power compared to competing FPGAs of a similar class. In addition, CrossLink-NX has a Soft Error Rate (SER) up to 100 times lower than similar FPGAs in its class, making it a compelling solution for mission-critical applications that must operate safely and reliably. The initial CrossLink-NX device is designed to support ruggedized environments found in outdoor, industrial, and automotive applications. CrossLink-NX delivers Instant on performance. This enables ultra-fast I/O configuration in 3 ms and total device configuration in less than 15 ms. It is available in a 6 x 6 mm form factor, which is up to ten times smaller than similar competing FPGAs in its class.

FPGAs optimized for automotive, high-security applications

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Lattice Semiconductor Corporation announced new versions of its MachXO3LF FPGAs for flexible deployment of robust automotive control applications and MachXO3D FPGAs for system security that support extended temperature operating ranges for automotive and other ruggedized applications. MachXO3D FPGAs augment the popular system control capabilities of the Lattice MachXO FPGA architecture with industry-leading security features, including hardware Root-of-Trust (RoT), platform firmware resilience (PFR), and secure dual-boot support. The MachXO3D and MachXO3LF devices target control, bridging, and I/O expansion applications that must operate reliably in rugged environments, including advanced driver assistance systems (ADAS), infotainment, motor control, 5G communications infrastructure, industrial robots and automation systems, and defense systems.

Emerging trends like electric vehicles (EVs), autonomous driving, ADAS, and infotainment are increasing OEMs’ reliance on electronic components in automotive systems. Deloitte projected that by 2030, 45 percent of the cost of a new car will come from electronic systems[1]. As more sensors and electric motors are incorporated into cars, systems become exposed to risk of malicious hacks. OEMs must be able to immediately detect vulnerabilities and combat cyberattacks, and they need electronic systems capable of reliable and secure operation in rugged environments.

The MachXO3D family of FPGAs builds on the MachXO3LF family of devices by adding a hardware security engine to help protect, detect, and recover the device from unauthorized attempts to access its firmware.

MachXO3LF and MachXO3D FPGAs are supported by Lattice’s integrated design software suite, Lattice Diamond®, a complete GUI-based FPGA design and verification environment with leading-edge design and implementation tools optimized for low-power Lattice FPGAs. The latest version of Lattice Diamond, version 3.11.3, is now available.

Key features of the new MachXO3LF and MachXO3D FPGA family include:

  • Support for an extended operating range -40°C to +125°C (junction temperature)
  • Robust control – provides instant-on control hub that reliably powers the platform up and power and simplifies deployment by:

o   Single 3.3V or 1.2V supply operation

o   Highest I/O-to-logic ratio

o   Enables deterministic I/O operation by eliminating power-up glitches with default pull-down and maintaining signal integrity with program slew rate, drive strength, and hysteresis.

FPGA IP aggregates multiple signals intoTDM signal occupying single inter-board wire

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Lattice Semiconductor Corporation announced a Single Wire Aggregation (SWA) IP solution for reducing overall system size and BOM cost in industrial, consumer, and computing applications. The solution is a quick, easy, and innovative way for developers to use low power, small form factor Lattice FPGAs to dramatically reduce the number of board-to-board and component-to-component connectors in their embedded designs to increase reliability and reduce overall system footprint and cost.

The connectors used to link circuit boards and modules in electronic systems are costly, take up valuable space in devices with tight form factors, and over time can degrade and negatively impact system reliability. Routing signals between multiple connectors on space-constrained circuit boards can create design challenges that increase overall time-to-market.

Featuring the extremely low power and small size Lattice iCE40 UltraPlus™ FPGA, the SWA solution provides the hardware and software developers require to implement a single wire interface capable of aggregating multiple common I/O (I2C, I2S, UART and GPIO) data streams between components and circuit boards in a system. Lattice currently offers the following aggregated I/O configurations in pre-configured bitstreams for fast application prototyping.

  • Two I2S, an I2C peripheral, an I2C controller, and eight GPIO signals
  • Six I2C controller and two GPIO signals
  • One I2C controller and 12 GPIO signals
  • Three I2C controller, two I2C peripheral, and 15 GPIO signals
  • One I2S, one I2C controller, one I2C peripheral, and eight GPIO signals

Lattice customers requiring customized configurations can source them directly from Lattice technical support at no charge.

The board is available for purchase at $249.00 from Lattice’s online store.

SoC prototyping system includes 300 M gates

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S2C introduces the new Quad 10M Prodigy Logic System equipped with four Stratix 10 GX 10M FPGA devices. Stratix 10 GX 10M FPGA is the world’s largest capacity FPGA device with 10.2M Logic Elements, 253Mb M20K memory, and 3,456 DSP blocks. Quad 10M Prodigy Logic System is an astounding 300 million equivalent ASIC gate prototyping solution with attractive cost-per-gate pricing.

  • Large capacity and scalability with 40.8M Logic Elements, 1,012Mb memory and 13,824 DSP blocks
  • 4,608 high-performance I/Os for inter FPGA connections and daughter cards
  • 160 high-speed transceivers that can run up to 16Gbps
  • Compatible with 90+ Prodigy Prototype Ready IPs
  • Integrated Multi-Debug Module
  • Compact, sleek, all-in-one chassis for clean, portable, and well-organized work environment

The increasing scale of SoC design demands a greater FPGA prototyping capacity in pre-silicon verifications. The Quad 10M Prodigy Logic System is equipped with four Intel 10M FPGA devices in a single chassis with unified power and control module. The newly designed control module has built-in debug hardware to enable high-performance deep trace capability for multiple FPGAs without extra peripherals. Enhanced partitioning tools can perform automatic intra-FPGA partition with DIB insertion between 10M dies and inter-FPGA partition using pin multiplexing over multiple FPGAs. The elegant systems design creates the fusion of complexity and easy-to-use.

The Quad 10M Prodigy Logic Systems work seamlessly with other Prodigy prototyping components such as Prodigy Player Pro software, Prodigy Multi-Debug Module and Prodigy ProtoBridge to provide unrivaled configuration, partitioning, deep-trace debug and co-modeling capabilities.

The Quad 10M Prodigy Logic System is available for purchase now.

Next-gen FPGAs bring low-power 16nm process to computational acceleration apps

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Trion Titanium FPGAsTrion Titanium FPGAs are fabricated on a 16nm process node and feature Efinix’s Quantum compute fabric. Inspired by the Quantum fabric underlying Efinix’s first-generation Trion FPGAs, the Quantum compute fabric adds additional compute and routing capability into its enhanced eXchangeable logic and routing (XLR) cells. Enhanced compute, united with the 3X clock frequency boost afforded by the 16nm process, make Trion Titanium FPGAs ideal for computational acceleration applications while the increased routing flexibility delivers unprecedented utilization ratios.

With the 16nm process node and the 2X efficiency improvement of the Quantum compute fabric, Titanium FPGAs pack loads of processing power into an extremely small die size, taking just a quarter of the area of the previous Trion generation. Additionally, the low power consumption of the 16nm node means that Titanium devices consume a third of the power of Trion devices and overcome all the thermal issues associated with highly integrated applications. This combination makes them ideal for multi-chip, system-in-package (SIP) designs such as those found in mobile, edge computing, AI and IoT.

The Titanium family comprises FPGAs ranging from 25K to 500K logic elements that are available in familiar and easy to mount BGA packages. The FPGAs have a range of hardened IP such as PCIe Gen4, DDR4, 10 Gbps Ethernet, and 2.5 Gbps MIPI controllers for optimum performance and seamless system connectivity in applications ranging from vision systems and industrial automation to edge computing.

DSP development software works with FPGAs

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DSP development softwareDSP development softwareMenta today announced the release of the new Menta Origami Programmer 2020.1, an enhanced version of the company’s innovative, robust and easy-to-use programming software.

The new Menta Origami Programmer 2020.1 can be demonstrated through webEx and evaluation licenses delivered through the Menta Starter Pack (MSP).

Also announced at Design Automation Conference (DAC) 2020, the virtual experience conference, is Menta’s Adaptive Digital Signal Processor (DSP) solution. The newly introduced Adaptive DSP solution can be inferred automatically using Menta Origami tool suite within the user’s embedded FPGA (eFPGA).

The Adaptive Menta DSP solution will allow users to implement the ideal DSP architecture within the eFPGA IP that better suits the hardware requirement. Operand size can be chosen for both the multiplier and the arithmetic logic unit (ALU).

The DSP block operating modes are programmable through the bitstream. It can dynamically be reconfigurable, and its behavior can be controlled at clock cycle level.

A Menta FIR generator empowers users to generate RTL code of an optimized FIR using Menta patented DSP FIR engine. The range of the FIR supported can be set between 4 and 512 taps, allowing users to define the number of DSP to use within their architecture as well as the data bus, and the ALU size, helping users meet frequency, area and latency goals.

DSP configuration is made easy through Origami Designer eFPGA IP software graphical interface and the adaptive DSP is automatically inferred by Origami Programmer synthesis.

Visitors to DAC 2020, a virtual experience, can learn more about Menta’s technological innovations at www.menta-efpga.com. A whitepaper about DSP is available upon request at: https://dac2020.pathable.co/organizations/5FbETpQuPPHBaRFcR.

 

FPGA-based prototyping systems employ Xilinx Virtex UltraScale+ chips

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FPGA-based prototyping systemsS2C has announced the availability of its new Prodigy S7 Series Logic Systems equipped with Xilinx’s Virtex UltraScale+™ FPGA devices. The Prodigy S7 is S2C’s 7th generation prototyping system designed and optimized for maximum performance and ease-of-use. With high DSP-to-logic and high memory-to-logic ratio, this family is the ideal platform for prototyping high-speed connectivity and computation-intensive applications. The first two members in the S7 series are the Prodigy S7-9P and Prodigy™ S7-13P.

S7-9P and S7-13P Logic System Highlights:

  • Supports 25Gbps transceivers
  • Up to 3.78M system logic cells, 455Mb internal memory, and 12,288 DSP slices
  • 676 high-performance I/Os and 48 GTY transceivers
  • 4x QSFP28 optical interfaces, each supporting 100G applications
  • Supports MIPI and x8 PCIe Gen4 / x8 PCIe Gen3 endpoint
  • Compatible with 90+ off-the-shelf S2C daughter cards
  • Abundant remote management capability

Today’s applications demand ever higher I/O throughputs as well as the need to interface with a variety of new standards. The Prodigy S7-9P and S7-13P Logic Systems are designed to assure highest signal integrity to support 25 Gbps transceivers and 1.4 Gbps general-purpose I/Os. The S7-9P and S7-13P are also equipped with an FMC connector to easily interface with 3rd party daughter cards, such as MIPI and AD/DA converters in addition to S2C’s 90+ daughter cards through standard Prodigy™ Connectors.

The Prodigy S7 Series Logic Systems work seamlessly with other Prodigy Prototyping components such as Prodigy Player Pro software, Prodigy™ Multi-Debug Module and Prodigy ProtoBridge to provide unrivaled configuration, partitioning, deep-trace debug and co-modeling capabilities.

The Prodigy S7-9P and S7-13P Logic Systems are for purchase now.

FPGAs provide high I/O Count in small form factor

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Lattice Semiconductor launched the new Lattice Certus-NX family of FPGAs. The devices lead the general-purpose FPGA market in I/O density, delivering up to twice the I/O density per mm2 in comparison to similar competing FPGAs, and provide best-in-class power savings, small size, reliability, instant-on performance, and support fast PCI Express (PCIe) and Gigabit Ethernet interfaces to enable data co-processing, signal bridging, and system control.

Certus-NX FPGAs target a range of applications, from data processing in automated industrial equipment to system management in communications infrastructure. The Certus-NX devices are the second family of FPGAs developed on the Lattice Nexus™ platform, the industry’s first low power FPGA platform using 28 nm FD-SOI process technology. With the launch of Certus-NX, Lattice marks the release of the second device family developed under Lattice’s new product development strategy in just six months.

Technology trends like industrial automation and 5G have developers across markets looking to add processing and connectivity to applications that operate at the network Edge. To successfully support these trends, devices require low power processing hardware with support for popular interfaces like PCIe and Gigabit Ethernet. Device developers also need easy-to-use development platforms from a single source that provide the hardware, software, and IP they need to get products to market quickly.

FPGA design tool supports SystemVerilog HDVL

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 Lattice Semiconductor Corporation announced the availability of the latest version of its popular software design tool for FPGAs, Lattice Radiant 2.1. The version includes support for the company’s new general-purpose Lattice Certus-NX FPGAs, the second family introduced within six months using Lattice Nexus FPGA development platform, plus native support for the SystemVerilog hardware description and verification language to increase functionality and design flexibility. Lattice Radiant design software accelerates development of Lattice FPGA-based applications for a range of markets, including industrial/automotive, communications/compute, and consumer.

The new version of Radiant supports SystemVerilog throughout the entire design flow, from the native synthesis tool through the schematic viewer, hierarchical viewer, configuration wizards, and debugging tool. This highly productive coding method simplifies on-chip debugging and other tasks to streamline the design process and get Lattice FPGA-based products to market faster. Lattice has made Radiant even easier to use as the tool’s drag-and-drop GUI has been redesigned with support for an I/O planner that enforces correct pin placement for each I/O signal or bus.

In comparison to design software offered by other FPGA vendors, Lattice Radiant provides best-in-class file size and download times. Radiant software is 20x smaller in file size and 10x faster to install than the competition, so customers can quickly download the tool and start designing their Lattice FPGA-based applications.

In addition to the Certus-NX family, Lattice Radiant also supports the CrossLink-NX FPGAs for embedded and smart visions applications, as well as the ultra-low power, small form factor Lattice iCE40 UltraPlus FPGAs.

Development tools for FPGA/eFPGA technology go open source

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QuickLogic Open Reconfigurable ComputingQuickLogic Corporation announced its  QORC (QuickLogic Open Reconfigurable Computing) initiative, making it the first programmable logic vendor to actively embrace a fully open source suite of development tools for its FPGA devices and eFPGA technology. This initiative engenders the emerging trend toward open source tooling, significantly broadens access to the company’s products, and enables both hardware and software developers with tools supported by both the user community and QuickLogic.

The company’s initial open source development tools, developed by Antmicro in collaboration with QuickLogic and Google, include complete support for its EOS S3 low power voice and sensor processing MCU with embedded FPGA, and its PolarPro 3E discrete FPGA family. Support for additional QuickLogic products, including QuickAI and support for its eFPGA IP offering will be added over the next few months.

EOS S3 Open Source Development Tools:

  • FPGA Development Flow: SymbiFlow – Open source tools for the optimization and automation of the FPGA design flow, from Verilog to bitstream generation. These tools enable innovation by making FPGAs more accessible to a broader community.
  • SoC Emulation: Renode – Antmicro’s Renode is an open source simulation framework for rapid prototyping, development and testing of multi-node systems. Utilizing Renode gives developers the flexibility to fully evaluate multiple development board applications.
  • Zephyr Real Time Operating System (RTOS) – The Zephyr RTOS is an open source, vendor-neutral, compact, real-time operating system running on the Arm® Cortex®-M4F for connected, resource-constrained and embedded devices in applications that require security and safety.
  • QuickFeather Development Kit – A small form factor, 100% open source hardware development kit ideal for the next generation of low-power Machine Learning (ML) capable IoT devices.

Traditionally, programmable logic vendors offered and supported only proprietary synthesis, place and route tools. Open source tools were relegated to hobbyists, academics, and independent consultants. However, the electronics industry is starting to see a shift toward open sourced hardware and software as it provides flexibility, vendor and community support, longevity, and adaptability to each engineer’s design flow. Google and Antmicro have been noteworthy influencers in this market, increasing the breadth of supported architectures and quality of results for the open source tools. They are now not only viable but desirable for the majority of the development community, including design teams at many of the industry’s largest companies.

SymbiFlow FPGA, Renode SoC Emulation, and Zephyr RTOS support are available now for QuickLogic’s EOS S3 voice and sensor processing platform and PolarPro 3E FPGA products, as well as the new QuickFeather Development Kit. Support for QuickLogic’s embedded FPGA technology will be added later this year.