Cadence Design Systems, Inc. has announced the availability of the industry’s only foundry-proven IC packaging design and analysis solutions for advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs. The new capabilities enable the faster multi-chip integration that is ideal for smaller, lighter and power-optimized wireless mobile devices.
This complete IC packaging design and analysis solution includes the Cadence OrbitIOTM Interconnect Designer, Cadence System-in-Package (SiP) Layout and Cadence Physical Verification System (PVS). This set of offerings enables multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.
The new Cadence SiP Layout WLCSP option integrated with PVS provides generic silicon wafer-based packaging methodologies previously validated by TSMC for their Integrated Fan-Out (InFO) process. Enhancements to OrbitIO Interconnect Designer strengthen 2.5D interposer package design support, providing optimal multi-die, single package interconnect integration. This enables higher performance for multi-substrate integrated devices with minimal size optimized for signal performance.