Agile Analog has launched its Digital Standard Cell Library (DSCL). It provides a comprehensive library of digital cells enabling designers to implement the digital circuits required to control analog blocks in mixed-signal solutions. The new digital library is available in thick-oxide-based cells, operating above the core voltage domain, minimizing leakage and allowing easy migration across different process nodes even in FINFET technologies.
The DSCL IP blocks can be optimized for low-power, ultra-low leakage, high density, or high-speed applications. There are options for channel length and various track heights to provide flexibility for designers. For specific design targets such as low-power designs, there is a special Power Management library. The library can be optimized for other PPA targets to ensure that customers have the best solution for their applications. It is also possible to generate models at customized PVT corners. The library has class-leading verification and is DFM-optimised.
Traditionally, analog IP blocks have to be manually redesigned for each application and process technology but Agile Analog has a unique way to automatically generate analog IP to exactly meet the customer’s specifications and process technology. Called Composa, it uses tried and tested analog IP circuits that are in the company’s Composa library. Effectively, the design-once-and-re-use-many-times model of digital IP now applies to analog IP for the first time. As the analog IP circuits in the Composa library have been extensively tested and used in previous designs, and are fully validated every time they are generated, this gives a similar level of reassurance to the digital IP world’s ‘silicon-proven’. All the major foundries are supported including TSMC, GlobalFoundries, Samsung Foundry, and SMIC as well as other IC foundries and manufacturers.
