Low-power LPDDR5X memory IP targets AI data centers

Cadence introduced an LPDDR5X memory IP system supporting data rates up to 9600 Mbps for enterprise and data center applications. The design combines LPDDR5X IP with symbol-based error correction to provide reliability comparable to DDR5 ECC while maintaining low power consumption and compact implementation.

The subsystem supports 40-bit channels and sideband ECC to preserve bandwidth while enabling fault detection and correction. Designed for AI and high-performance computing workloads, the solution delivers high memory throughput while improving energy efficiency compared to traditional DDR5 architectures. It is delivered as a complete subsystem to simplify integration into data center SoCs and accelerator platforms.