Now available for SoC designs: 112G Ethernet PHY IP

Synopsys announced its DesignWare 112G Ethernet PHY IP on TSMC’s N7 process supporting true long-reach channels for up to 800G networking applications. The DesignWare 112G PHY, based on Synopsys’ silicon-proven 56G Ethernet PHY available in multiple FinFET processes, delivers PAM-4 signaling for more than 35dB channel loss across optical, copper cables, and backplane interconnects. The 112G PHY’s unique transmit phase-locked loop architecture allows independent, per lane data rates for a broad range of high-throughput protocols and applications.

To maximize bandwidth and beachfront density, the 112G PHY’s flexible layout allows placement of square macros in a multi-row structure and along all edges of the die. Combined with Synopsys’ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 112G Ethernet PHY solution for fast, reliable integration into hyperscale data center SoCs. The DesignWare 112G Ethernet PHY extends Synopsys’ portfolio of IP for cloud computing applications, including widely-used protocols such as PCI Express, DDR, HBM, CCIX, and more.

The 112G Ethernet PHY incorporates Synopsys’ silicon-proven data converters, and implements power scaling techniques for up to 20 percent power reduction in low-loss channels. The comprehensive test features, including embedded bit-error rate tester and internal eye monitor, provide on-chip testability and visibility into channel performance. The 112G Ethernet PHY delivers robust performance across voltage and temperature variations using continuous calibration and adaptation algorithms.

The DesignWare 112G Ethernet PHY for TSMC’s N7 process is scheduled to be available in Q1 of 2020.