Synopsys has unveiled Fusion Compiler, an innovative RTL-to-GDSII product that enables a new era in digital design implementation. By fusing a novel high-capacity synthesis technology with the IC Compiler II industry-leading place-and-route technology, Fusion Compiler offers new levels of predictable quality-of-results (QoR) to address the challenges presented by the industry’s most advanced designs. This unified architecture shares technologies across the RTL-to-GDSII flow to enable a highly convergent system delivering 20 percent better QoR and 2X faster time-to-results (TTR).

Fusion Compiler is tapeout-validated at market-leading semiconductor companies and has been proven to deliver the highest-quality designs. Fusion Compiler also enables a single cockpit for RTL-to-GDSII implementation, enabling unparalleled levels of design productivity, flexibility, and throughput to maximize power, performance, and area (PPA) for the most challenging designs.

“Enablement of the next generation of market-shaping products has demanded the reassessment of how design productivity and quality-of-results can be improved,” said Sassine Ghazi, co-general manager of the Design Group at Synopsys. “Leveraging the leading technologies from IC Compiler II and fusing novel, high-capacity synthesis and our industry-leading golden signoff technologies onto the same scalable data model, Fusion Compiler is engineered to offer the best QoR in the shortest time.”

Fusion Compiler is built on a single, highly-scalable data model that supports common signoff analysis, optimization, concurrent clock data optimization, clock topology creation, and routing engines. These best-in-class engines form a single unified optimization framework that is central to Fusion Compiler’s predictable flow. Its architecture also enables sharing of advanced technologies across the RTL-to-GDSII design flow. Technologies previously used only in place-and-route can now be applied during synthesis, and vice versa, enabling new levels of timing, power, and area.