Synopsys, Inc. unveiled its Fusion Technology that transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff tools, enabling designers to accelerate the delivery of their next-generation designs with full-flow quality-of-results (QoR) and the fastest time-to-results (TTR). It redefines conventional EDA tool boundaries across synthesis, place-and-route and signoff, sharing engines across the industry’s premier digital design tools, and using a unique, Fusion data model for both logical and physical representation.
Fusion Technology enables one DNA backbone across the Synopsys Design Platform that includes IC Compiler II place-and-route, Design Compiler Graphical synthesis, PrimeTime signoff, StarRC extraction, IC Validator physical verification, DFTMAX test, TetraMAX II automatic test pattern generation (ATPG), SpyGlass DFT ADV RTL testability analysis, and Formality equivalence checking solutions. It provides Design Fusion, ECO Fusion, Signoff Fusion, and Test Fusion, resulting in the most predictable RTL-to-GDSII flow with the fewest iterations, as well as unsurpassed design frequency, power, and area.
The traditional RTL-to-GDSII design flow has clear lines of demarcation between synthesis, place-and-route, and signoff functions. These functional boundaries cause rework when transitioning from one design phase to the next, as the less-precise engines used early in the flow are replaced by more-precise engines closer to tapeout. Design iterations at the transition point between tools lead to degraded full-flow TTR and unmet power, performance, and area (PPA) targets.
Fusion Technology redefines conventional EDA tool boundaries and enables Design Fusion, ECO Fusion, Signoff Fusion, and Test Fusion. Design Fusion provides common engines between synthesis and place-and-route to enable convergence, and moves synthesis optimization technology into place-and-route, and place-and-route optimization technology into synthesis in order to enable best QoR. ECO Fusion drives faster signoff closure based on PrimeTime and StarRC golden signoff analysis inside implementation, improving flow predictability and eliminating ECO iterations. Signoff Fusion eliminates excessive design margin and overdesign, using the golden signoff backbone for both optimization and signoff, to enable perfect correlation, reduced pessimism, and superior QoR. Test Fusion is the combination of design-for-test RTL analysis and design-for-test synthesis integrated into implementation, enabling best QoR while reducing silicon test costs and turnaround time.
Learn more about Fusion Technology and the unique Design Fusion, ECO Fusion, Signoff Fusion, and Test Fusion capabilities in this whitepaper.
Early-adoption customers and our exclusive rail analysis partner, ANSYS, will discuss their experiences and results using Fusion Technology at the Synopsys Users Group(SNUG) Silicon Valley event, March 21-22, at the Santa Clara Convention Center in Santa Clara, Calif.