SLX for FPGA is a new programming tool to support the increasing use of FPGAs for embedded computing tasks such as sensor fusion and deep learning. It has been developed in partnership with customers who will use the solution for automotive, industrial automation and defense projects.
We believe this to be the first time that a programming tool offers a complete, industry-grade exploration of the design space to optimize hardware/software partitioning on FPGAs. In addition, the automatic insertion of pragmas and code rewriting are features that can simplify how applications are delivered to FPGAs and significantly reduce project times. It is fully compatible with Xilinx SDSoC and Vivado tools and we continue to increase the available options for you.
SLX combines a deep understanding of source code, how it is executed and the implications of a system that enables the partitioning of applications into software to run on several processors, and hardware to be mapped to an FPGA.
It gives comprehensive processor modeling, and characterization of the timing and resource capabilities of the FPGA. SLX searches for parallelism patterns from static and dynamic information.
The design space is explored to fully optimize hardware/software partitioning. Pragmas are automatically inserted based on the optimization decisions for the parallelization of the software and for guiding the High Level Synthesis (HLS) process for the hardware implementation. SLX uniquely connects its analysis and advice to your source code, simplifying your task of understanding the opportunities for, or blockers of, parallelism and hardware acceleration.